_primary.vhd

来自「Full AES Simulation Code」· VHDL 代码 · 共 21 行

library verilog;
use verilog.vl_types.all;
entity COREAES128 is
    port(
        NRESET          : in     vl_logic;
        CLK             : in     vl_logic;
        EN              : in     vl_logic;
        CLR             : in     vl_logic;
        ED              : in     vl_logic;
        D               : in     vl_logic_vector(127 downto 0);
        K               : in     vl_logic_vector(31 downto 0);
        KSEL            : in     vl_logic_vector(1 downto 0);
        KWR             : in     vl_logic;
        KEXP            : in     vl_logic;
        Q               : out    vl_logic_vector(127 downto 0);
        QVAL            : out    vl_logic;
        READY           : out    vl_logic;
        KRDY            : out    vl_logic
    );
end COREAES128;