_primary.vhd

Full AES Simulation Code

library verilog;
use verilog.vl_types.all;
entity USER_COREAES128 is
    port(
        NRESET          : in     vl_logic;
        CLK             : in     vl_logic;
        EN              : in     vl_logic;
        WR              : in     vl_logic;
        DIN             : in     vl_logic_vector(15 downto 0);
        CTRL            : in     vl_logic_vector(3 downto 0);
        DSEL            : in     vl_logic_vector(2 downto 0);
        DOUT            : out    vl_logic_vector(15 downto 0);
        QVAL            : out    vl_logic;
        READY           : out    vl_logic;
        KRDY            : out    vl_logic
    );
end USER_COREAES128;