i8051.cc.txt

8051的IP,采用VHDL语言描述,支持intel的HEX格式,包括中断,定时器等.

			os << "\t" << "RAM(" << (int)(ROM[PC+1]) << ") <- RAM(" 
			   << (unsigned int)(unsigned char)(ROM[PC]) << ")" << endl;
		    #endif
		    #endif
		    directAddr = ROM[PC++];
		    IR = ROM[PC++];
		    RAM[(IR<128) ? IR : (IR+128)] = 
			RAM[(directAddr < 128) ? directAddr : (directAddr+128)];
		    cycleCount += 24;
		    break;
		    
		    // direct <- ((Ri))
		case MOV11:
		    
		    #ifdef DEBUG
			os << "MOV 11" << endl;
		    #ifdef DETAIL
			os << "\t" << "RAM(" << (unsigned int)(unsigned char)(ROM[PC]) << ") <- RAM(R" 
			   << (int)(IR & 0x01) << ")" << endl;
		    #endif
		    #endif
		    regNum = IR & 0x01;
		    IR = ROM[PC++];
		    RAM[(IR <128) ? IR : (IR+128)] = 
			RAM[RAM[GetRegisterBank()+regNum]];
		    cycleCount += 24;
		    break;
		    
		    // direct <- #data
		case MOV12:
		    
		    #ifdef DEBUG
			os << "MOV 12" << endl;
		    #ifdef DETAIL
			os << "\t" << "RAM(" << (unsigned int)(unsigned char)(ROM[PC]) << ") <- ";
			PrintHex(ROM[PC], &os);
			os << endl;
		    #endif
		    #endif
		    directAddr = ROM[PC++];
		    IR = ROM[PC++];
		    RAM[(directAddr<128) ? directAddr : (directAddr+128)] = 
			(char)IR;
		    cycleCount += 24;
		    break;
		    
		    // Ri <- A
		case MOV13:
		    
		    #ifdef DEBUG
			os << "MOV 13" << endl;
		    #ifdef DETAIL
			os << "\t" << "RAM(R" << (int)(IR & 0x01) << ") <- A" << endl;
		    #endif
		    #endif
		    regNum = IR & 0x01;
		    RAM[RAM[GetRegisterBank()+regNum]] = RAM[ACC];
		    cycleCount += 12;
		    break;
		    
		    // Ri <- direct
		case MOV14:
		    
		    #ifdef DEBUG
			os << "MOV 14" << endl;
		    #ifdef DETAIL
			os << "\t" << "RAM(R" << (int)(IR & 0x01) << ") <- RAM(" 
			   << (unsigned int)(unsigned char)(ROM[PC]) << ")" << endl;
		    #endif
		    #endif
		    regNum = IR & 0x01;
		    IR = ROM[PC++];
		    RAM[RAM[GetRegisterBank()+regNum]] = 
			RAM[(IR<128) ? IR : (IR+128)];
		    cycleCount += 24;
		    break;
		    
		    // @Ri, #data
		case MOV15:
		    
		    #ifdef DEBUG
			os << "MOV 15" << endl;
		    #ifdef DETAIL
			os << "\t" << "RAM(R" << (int)(IR & 0x01) << ") <- ";
			PrintHex(ROM[PC], &os);
			os << endl;
		    #endif
		    #endif
		    regNum = IR & 0x01;
		    IR = ROM[PC++];;
		    RAM[RAM[GetRegisterBank()+regNum]] = (char)IR;
		    cycleCount += 12;
		    break;
		    
		    // MOV (C), bit
		case MOV16:
		    
		    #ifdef DEBUG
			os << "MOV 16" << endl;
		    #ifdef DETAIL
			os << "\t" << "C <- RAM(" 
			   << (int)(((ROM[PC] & 0xF8) < 128) ? 
				    (((ROM[PC] & 0xF8)>>3)+32) : (128 + (ROM[PC] & 0xF8)))
			   << ")." << (int)(ROM[PC] & 0x07) << endl;
		    #endif
		    #endif
		    IR = ROM[PC++];
		    if( GetBit(RAM[((IR & 0xF8) < 128) ? 
				  (((IR & 0xF8)>>3)+32) : 
				  (128 + (IR & 0xF8))], (IR & 0x07)) == 0x01 ) {
			SetBit(RAM[PSW], CY);
		    }
		    else {
			ClearBit(RAM[PSW], CY);
		    }
		    cycleCount += 12;
		    break;
		    
		    // MOV bit, (C)
		case MOV17:
		    
		    #ifdef DEBUG
			os << "MOV 17" << endl;
		    #ifdef DETAIL
			os << "\t" << "RAM(" 
			   << (int)(((ROM[PC] & 0xF8) < 128) ? 
				    (((ROM[PC] & 0xF8)>>3)+32) : (128 + (ROM[PC] & 0xF8)))
			   << ")." << (int)(ROM[PC] & 0x07)
			   << " <- C" << endl;
		    #endif
		    #endif
		    IR = ROM[PC++];
		    if( GetBit(RAM[PSW], CY) == 0x01 ) {
			SetBit(RAM[((IR & 0xF8) < 128) ? 
				  (((IR & 0xF8)>>3)+32) : 
				  (128 + (IR & 0xF8))], (IR & 0x07));
		    }
		    else {
			ClearBit(RAM[((IR & 0xF8) < 128) ? 
				    (((IR & 0xF8)>>3)+32) : 
				    (128 + (IR & 0xF8))], (IR & 0x07));
		    }
		    cycleCount += 24;
		    break;
		    
		    // MOV DPTR, data16
		case MOV18:
		    
		    #ifdef DEBUG
			os << "MOV 18" << endl;
		    #ifdef DETAIL
			((unsigned char*)&tempDPTR)[1] = ROM[PC];
			((unsigned char*)&tempDPTR)[0] = ROM[PC+1];
			os << "\t" << "DPTR <- " << tempDPTR << endl;
		    #endif
		    #endif
		    RAM[DPH] = ROM[PC++];
		    RAM[DPL] = ROM[PC++];
		    cycleCount += 24;
		    break;
		    
		    // MOVC (A), @A+DPTR
		case MOVC1:
		    
		    #ifdef DEBUG
			os << "MOVC 1" << endl;
		    #ifdef DETAIL
			os << "\t" << "A <- ROM(A+DPTR)" << endl;
		    #endif
		    #endif
		    ((unsigned char*)&tempDPTR)[1] = RAM[DPH];
		    ((unsigned char*)&tempDPTR)[0] = RAM[DPL];
		    RAM[ACC] = ROM[(unsigned short)RAM[ACC]+tempDPTR];
		    cycleCount += 24;
		    break;
		    
		    // MOVC (A), @A+PC
		case MOVC2:
		    
		    #ifdef DEBUG
			os << "MOVC 2" << endl;
		    #ifdef DETAIL
			os << "\t" << "A <- ROM(A+PC)" << endl;
		    #endif
		    #endif
		    RAM[ACC] = ROM[(unsigned char)RAM[ACC]+PC];
		    cycleCount += 24;
		    break;
		    
		    // ADD A, (Rn)
		case ADD1:
		    
		    #ifdef DEBUG
			os << "ADD 1" << endl;
		    #ifdef DETAIL
			os << "\t" << "A <- A + R" << (int)(IR & 0x07) << endl;
		    #endif
		    #endif
		    carry3 = false;
		    carry6 = false;
		    carry7 = false;
		    regNum = IR & 0x07;
		    tempAdd = (RAM[ACC] & 0x0F) + 
			(RAM[GetRegisterBank()+regNum] & 0x0F);
		    if( (tempAdd & 0x0010) == 0x0010 ) carry3 = true;
		    tempAdd += (RAM[ACC] & 0x70) + 
			(RAM[GetRegisterBank()+regNum] & 0x70);
		    if( (tempAdd & 0x0080) == 0x0080 ) carry6 = true;
		    tempAdd += (RAM[ACC] & 0x80) + 
			(RAM[GetRegisterBank()+regNum] & 0x80);
		    if( (tempAdd & 0x0100) == 0x0100 ) carry7 = true;
		    RAM[ACC] = tempAdd;
		    if( carry3 ) SetBit(RAM[PSW], AC);
		    else ClearBit(RAM[PSW], AC);
		    if( carry7 ) SetBit(RAM[PSW], CY);
		    else ClearBit(RAM[PSW], CY);
		    if( (carry6 && !carry7) || (!carry6 && carry7) ) 
			SetBit(RAM[PSW], OV);
		    else ClearBit(RAM[PSW], OV);
		    cycleCount += 12;
		    break;
		    
		    // ADD A, (direct)
		case ADD2:
		    
		    #ifdef DEBUG
			os << "ADD 2" << endl;
		    #ifdef DETAIL
			os << "\t" << "A <- A + RAM(" << (unsigned int)(unsigned char)(ROM[PC]) << ")" << endl;
		    #endif
		    #endif
		    carry3 = false;
		    carry6 = false;
		    carry7 = false;
		    IR = ROM[PC++];
		    tempAdd = (RAM[ACC] & 0x0F) + 
			(RAM[IR <128 ? IR : (IR+128)] & 0x0F);
		    if( (tempAdd & 0x0010) == 0x0010 ) carry3 = true;
		    tempAdd += (RAM[ACC] & 0x70) + 
			(RAM[IR <128 ? IR : (IR+128)] & 0x70);
		    if( (tempAdd & 0x0080) == 0x0080 ) carry6 = true;
		    tempAdd += (RAM[ACC] & 0x80) + 
			(RAM[IR <128 ? IR : (IR+128)] & 0x80);
		    if( (tempAdd & 0x0100) == 0x0100 ) carry7 = true;
		    RAM[ACC] = tempAdd;
		    if( carry3 ) SetBit(RAM[PSW], AC);
		    else ClearBit(RAM[PSW], AC);
		    if( carry7 ) SetBit(RAM[PSW], CY);
		    else ClearBit(RAM[PSW], CY);
		    if( (carry6 && !carry7) || (!carry6 && carry7) ) 
			SetBit(RAM[PSW], OV);
		    else ClearBit(RAM[PSW], OV);
		    cycleCount += 12;
		    break;
		    
		    // ADD A, ((Ri))
		case ADD3:
		    
		    #ifdef DEBUG
			os << "ADD 3" << endl;
		    #ifdef DETAIL
			os << "\t" << "A <- A + RAM(R" << (int)(IR & 0x01) << ")" << endl;
		    #endif
		    #endif
		    carry3 = false;
		    carry6 = false;
		    carry7 = false;
		    regNum = IR & 0x01;
		    tempAdd = (RAM[ACC] & 0x0F) + 
			(RAM[RAM[GetRegisterBank()+regNum]] & 0x0F);
		    if( (tempAdd & 0x0010) == 0x0010 ) carry3 = true;
		    tempAdd += (RAM[ACC] & 0x70) + 
			(RAM[RAM[GetRegisterBank()+regNum]] & 0x70);
		    if( (tempAdd & 0x0080) == 0x0080 ) carry6 = true;
		    tempAdd += (RAM[ACC] & 0x80) + 
			(RAM[RAM[GetRegisterBank()+regNum]] & 0x80);
		    if( (tempAdd & 0x0100) == 0x0100 ) carry7 = true;
		    RAM[ACC] = tempAdd;
		    if( carry3 ) SetBit(RAM[PSW], AC);
		    else ClearBit(RAM[PSW], AC);
		    if( carry7 ) SetBit(RAM[PSW], CY);
		    else ClearBit(RAM[PSW], CY);
		    if( (carry6 && !carry7) || (!carry6 && carry7) ) 
			SetBit(RAM[PSW], OV);
		    else ClearBit(RAM[PSW], OV);
		    cycleCount += 12;
		    break;
		    
		    // ADD A, (#data)
		case ADD4:
		    
		    #ifdef DEBUG
			os << "ADD 4" << endl;
		    #ifdef DETAIL
			os << "\t" << "A <- A + ";
			PrintHex(ROM[PC], &os);
			os << endl;
		    #endif
		    #endif
		    carry3 = false;
		    carry6 = false;
		    carry7 = false;
		    IR = ROM[PC++];
		    tempAdd = (RAM[ACC] & 0x0F) + ((char)IR & 0x0F);
		    if( (tempAdd & 0x0010) == 0x0010 ) carry3 = true;
		    tempAdd += (RAM[ACC] & 0x70) + ((char)IR & 0x70);
		    if( (tempAdd & 0x0080) == 0x0080 ) carry6 = true;
		    tempAdd += (RAM[ACC] & 0x80) + ((char)IR & 0x80);
		    if( (tempAdd & 0x0100) == 0x0100 ) carry7 = true;
		    RAM[ACC] = tempAdd;
		    if( carry3 ) SetBit(RAM[PSW], AC);
		    else ClearBit(RAM[PSW], AC);
		    if( carry7 ) SetBit(RAM[PSW], CY);
		    else ClearBit(RAM[PSW], CY);
		    if( (carry6 && !carry7) || (!carry6 && carry7) ) 
			SetBit(RAM[PSW], OV);
		    else ClearBit(RAM[PSW], OV);
		    cycleCount += 12;
		    break;
		    
		    // ADDC A, (Rn)
		case ADDC1:
		    
		    #ifdef DEBUG
			os << "ADDC 1" << endl;
		    #ifdef DETAIL
			os << "\t" << "A <- A + R" << (int)(IR & 0x07) << " + C" << endl;
		    #endif
		    #endif
		    carry3 = false;
		    carry6 = false;
		    carry7 = false;
		    regNum = IR & 0x07;
		    tempAdd = (RAM[ACC] & 0x0F) + 
			(RAM[GetRegisterBank()+regNum] & 0x0F) + 
			(char)GetBit(RAM[PSW], CY);
		    if( (tempAdd & 0x0010) == 0x0010 ) carry3 = true;
		    tempAdd += (RAM[ACC] & 0x70) + 
			(RAM[GetRegisterBank()+regNum] & 0x70);
		    if( (tempAdd & 0x0080) == 0x0080 ) carry6 = true;
		    tempAdd += (RAM[ACC] & 0x80) + 
			(RAM[GetRegisterBank()+regNum] & 0x80);
		    if( (tempAdd & 0x0100) == 0x0100 ) carry7 = true;
		    RAM[ACC] = (unsigned char)(tempAdd & 0x00FF);
		    if( carry3 ) SetBit(RAM[PSW], AC);
		    else ClearBit(RAM[PSW], AC);
		    if( carry7 ) SetBit(RAM[PSW], CY);
		    else ClearBit(RAM[PSW], CY);
		    if( (carry6 && !carry7) || (!carry6 && carry7) ) 
			SetBit(RAM[PSW], OV);
		    else ClearBit(RAM[PSW], OV);
		    cycleCount += 12;
		    break;
		    
		    // ADDC A, (direct)
		case ADDC2:
		    
		    #ifdef DEBUG
			os << "ADDC 2" << endl;
		    #ifdef DETAIL
			os << "\t" << "A <- A + RAM(" << (unsigned int)(unsigned char)(ROM[PC]) << ") + C" << endl;
		    #endif
		    #endif
		    carry3 = false;
		    carry6 = false;
		    carry7 = false;
		    IR = ROM[PC++];
		    tempAdd = (RAM[ACC] & 0x0F) + 
			(RAM[IR <128 ? IR : (IR+128)] & 0x0F) +
			(char)GetBit(RAM[PSW], CY);
		    if( (tempAdd & 0x0010) == 0x0010 ) carry3 = true;
		    tempAdd += (RAM[ACC] & 0x70) + 
			(RAM[IR <128 ? IR : (IR+128)] & 0x70);
		    if( (tempAdd & 0x0080) == 0x0080 ) carry6 = true;
		    tempAdd += (RAM[ACC] & 0x80) + 
			(RAM[IR <128 ? IR : (IR+128)] & 0x80);
		    if( (tempAdd & 0x0100) == 0x0100 ) carry7 = true;
		    RAM[ACC] = (unsigned char)(tempAdd & 0x00FF);
		    if( carry3 ) SetBit(RAM[PSW], AC);
		    else ClearBit(RAM[PSW], AC);
		    if( carry7 ) SetBit(RAM[PSW], CY);
		    else ClearBit(RAM[PSW], CY);
		    if( (carry6 && !carry7) || (!carry6 && carry7) ) 
			SetBit(RAM[PSW], OV);
		    else ClearBit(RAM[PSW], OV);
		    cycleCount += 12;
		    break;
		    
		    // ADDC A, ((Ri))
		case ADDC3:
		    
		    #ifdef DEBUG
			os << "ADDC 3" << endl;
		    #ifdef DETAIL
			os << "\t" << "A <- A + RAM(R" << (int)(IR & 0x01) << ") + C" << endl;
		    #endif
		    #endif
		    carry3 = false;
		    carry6 = false;
		    carry7 = false;
		    regNum = IR & 0x01;
		    tempAdd = (RAM[ACC] & 0x0F) + 
			(RAM[RAM[GetRegisterBank()+regNum]] & 0x0F) + 
			(char)GetBit(RAM[PSW], CY);
		    if( (tempAdd & 0x0010) == 0x0010 ) carry3 = true;
		    tempAdd += (RAM[ACC] & 0x70) + 
			(RAM[RAM[GetRegisterBank()+regNum]] & 0x70);
		    if( (tempAdd & 0x0080) == 0x0080 ) carry6 = true;
		    tempAdd += (RAM[ACC] & 0x80) + 
			(RAM[RAM[GetRegisterBank()+regNum]] & 0x80);
		    if( (tempAdd & 0x0100) == 0x0100 ) carry7 = true;
		    RAM[ACC] = (unsigned char)(tempAdd & 0x00FF);
		    if( carry3 ) SetBit(RAM[PSW], AC);
		    else ClearBit(RAM[PSW], AC);
		    if( carry7 ) SetBit(RAM[PSW], CY);
		    else ClearBit(RAM[PSW], CY);
		    if( (carry6 && !carry7) || (!carry6 && carry7) ) 
			SetBit(RAM[PSW], OV);
		    else ClearBit(RAM[PSW], OV);
		    cycleCount += 12;
		    break;
		    
		    // ADDC A, (#data)
		case ADDC4:
		    
		    #ifdef DEBUG
			os << "ADDC 4" << endl;
		    #ifdef DETAIL
			os << "\t" << "A <- A + ";
			PrintHex(ROM[PC], &os);
			os << " + C" << endl;
		    #endif
		    #endif
		    carry3 = false;
		    carry6 = false;
		    carry7 = false;
		    IR = ROM[PC++];
		    tempAdd = (RAM[ACC] & 0x0F) + 
			(IR & 0x0F) + GetBit(RAM[PSW], CY);
		    if( (tempAdd & 0x0010) == 0x0010 ) carry3 = true;
		    tempAdd += (RAM[ACC] & 0x70) + (IR & 0x70);
		    if( (tempAdd & 0x0080) == 0x0080 ) carry6 = true;
		    tempAdd += (RAM[ACC] & 0x80) + (IR & 0x80);
		    if( (tempAdd & 0x0100) == 0x0100 ) carry7 = true;
		    RAM[ACC] = (unsigned char)(tempAdd & 0x00FF);
		    if( carry3 ) SetBit(RAM[PSW], AC);
		    else ClearBit(RAM[PSW], AC);
		    if( carry7 ) SetBit(RAM[PSW], CY);
		    else ClearBit(RAM[PSW], CY);
		    if( (carry6 && !carry7) || (!carry6 && carry7) ) 
			SetBit(RAM[PSW], OV);
		    else ClearBit(RAM[PSW], OV);
		    cycleCount += 12;
		    break;
		    
		    // SUBB (A), (Rn)
		case SUBB1:
		    
		    #ifdef DEBUG
			os << "SUBB 1" << endl;
		    #ifdef DETAIL
			os << "\t" << "A <- A - R" << (int)(IR & 0x07) << " - C" << endl;
		    #endif
		    #endif
		    borrow3 = false;
		    borrow6 = false;
		    borrow7 = false;
		    regNum = IR & 0x07;
		    if( (unsigned char)(RAM[ACC] & 0x0F) <
			(unsigned char)((RAM[GetRegisterBank()+regNum] & 0x0F) +  
					(char)GetBit(RAM[PSW], CY)) ) {
			borrow3 = true;
		    } 
		    if( (unsigned char)(RAM[ACC] & 0x7F) <
			(unsigned char)((RAM[GetRegisterBank()+regNum] & 0x7F) + 
					(char)GetBit(RAM[PSW], CY)) ) {
			borrow6 = true;
		    }
		    if( (unsigned char)RAM[ACC] <
			(unsigned char)(RAM[GetRegisterBank()+regNum] + 
					(char)GetBit(RAM[PSW], CY)) ) {
			borrow7 = true;
		    }
		    RAM[ACC] = RAM[ACC] - 
			(RAM[GetRegisterBank()+regNum] + (char)GetBit(RAM[PSW], CY));
		    if( borrow3 ) SetBit(RAM[PSW], AC);
		    else ClearBit(RAM[PSW], AC);
		    if( borrow7 ) SetBit(RAM[PSW], CY);
		    else ClearBit(RAM[PSW], CY);
		    if( (borrow6 && !borrow7) || (!borrow6 && borrow7) ) 
			SetBit(RAM[PSW], OV);
		    else ClearBit(RAM[PSW], OV);
		    cycleCount += 12;
		    break;
		    
		    // SUBB (A), direct
		case SUBB2:
		    
		    #ifdef DEBUG
			os << "SUBB 2" << endl;
		    #ifdef DETAIL
			os << "\t" << "A <- A - RAM(" << (unsigned int)(unsigned char)(ROM[PC]) << ") - C" << endl;
		    #endif
		    #endif
		    borrow3 = false;
		    borrow6 = false;
		    borrow7 = false;
		    IR = ROM[PC++];
		    if( (unsigned char)(RAM[ACC] & 0x0F) <
			(unsigned char)((RAM[IR <128 ? IR : (IR+128)] & 0x0F) + 
			 (char)GetBit(RAM[PSW], CY)) ) {
			borrow3 = true;
		    }
		    if( (unsigned char)(RAM[ACC] & 0x7F) <
			(unsigned char)((RAM[IR <128 ? IR : (IR+128)] & 0x7F) + 
			 (char)GetBit(RAM[PSW], CY)) ) {
			borrow6 = true;
		    }
		    if( (unsigned char)RAM[ACC] <
			(unsigned char)(RAM[IR <128 ? IR : (IR+128)] + 
			 (char)GetBit(RAM[PSW], CY)) ) {
			borrow7 = true;
		    }
		    RAM[ACC] = RAM[ACC] - 
			(RAM[IR <128 ? IR : (IR+128)] + 
				 (char)GetBit(RAM[PSW], CY));
		    if( borrow3 ) SetBit(RAM[PSW], AC);
		    else ClearBit(RAM[PSW], AC);
		    if( borrow7 ) SetBit(RAM[PSW], CY);
		    else ClearBit(RAM[PSW], CY);
		    if( (borrow6 && !borrow7) || (!borrow6 && borrow7) ) 
			SetBit(RAM[PSW], OV);
		    else ClearBit(RAM[PSW], OV);
		    cycleCount += 12;
		    break;
		    
		    // SUBB (A), ((Ri))
		case SUBB3:
		    
		    #ifdef DEBUG
			os << "SUBB 3" << endl;
		    #ifdef DETAIL
			os << "\t" << "A <- A - RAM(R" << (int)(IR & 0x01) << ") - C" << endl;
		    #endif
		    #endif
		    borrow3 = false;
		    borrow6 = false;
		    borrow7 = false;
		    regNum = IR & 0x01;
		    if( (unsigned char)(RAM[ACC] & 0x0F) <
			(unsigned char)((RAM[RAM[GetRegisterBank()+regNum]] & 0x0F) + 
			 (char)GetBit(RAM[PSW], CY)) ) {
			borrow3 = true;