i8051.cc.txt

8051的IP,采用VHDL语言描述,支持intel的HEX格式,包括中断,定时器等.

		case INC2:
		    
		    #ifdef DEBUG
			os << "INC 2" << endl;
		    #ifdef DETAIL
			os << "\t" << "R" << (int)(IR & 0x07) << "++" << endl;
		    #endif
		    #endif
		    regNum = IR & 0x07;
		    RAM[GetRegisterBank()+regNum]++;
		    cycleCount += 12;
		    break;
		    
		    // INC (direct)
		case INC3:
		    
		    #ifdef DEBUG
			os << "INC 3" << endl;
		    #ifdef DETAIL
			os << "\t" << "RAM(" << (unsigned int)(unsigned char)ROM[PC] << ")++" << endl; 
		    #endif
		    #endif
		    IR = ROM[PC++];
		    RAM[IR < 128 ? IR : (IR+128)]++;
		    cycleCount += 12;
		    break;
		    
		    // INC ((Ri))
		case INC4:
		    
		    #ifdef DEBUG
			os << "INC 4" << endl;
		    #ifdef DETAIL
			os << "\t" << "RAM(R" << (int)(IR & 0x01) << ")++" << endl; 
		    #endif
		    #endif
		    regNum = IR & 0x01;
		    RAM[RAM[GetRegisterBank()+regNum]]++;
		    cycleCount += 12;
		    break;
		    
		    // INC (DPTR)
		case INC5:
		    
		    #ifdef DEBUG
			os << "INC 5" << endl;
		    #ifdef DETAIL
			os << "\t" << "DPTR++" << endl;
		    #endif
		    #endif
		    ((unsigned char*)&tempDPTR)[1] = RAM[DPH];
		    ((unsigned char*)&tempDPTR)[0] = RAM[DPL];
		    tempDPTR++;
		    RAM[DPH] = ((unsigned char*)&tempDPTR)[1];
		    RAM[DPL] = ((unsigned char*)&tempDPTR)[0];
		    cycleCount += 24;
		    break;
		    
		    // NOP
		case NOP:
		    
		    #ifdef DEBUG
			os << "NOP" << endl;
		    #ifdef DETAIL
			os << "\t" << "nothing" << endl;
		    #endif
		    #endif
		    // no code
		    cycleCount += 12;
		    break;
		    
		    // DJNZ (Rn), (rel)  
		case DJNZ1:
		    
		    #ifdef DEBUG
			os << "DJNZ 1" << endl;
		    #ifdef DETAIL
			os << "\t" << "R" << (int)(IR & 0x07) << "--" << endl;
			os << "\t" << "if( R" <<  (int)(IR & 0x07)
			   << " != 0 ) JMP " 
			   << (PC+(unsigned int)(unsigned char)ROM[PC]+1) << endl;			
		    #endif
		    #endif
		    regNum = IR & 0x07;
		    RAM[GetRegisterBank()+regNum] = 
			(unsigned char)RAM[GetRegisterBank()+regNum] - 1;
		    if( RAM[GetRegisterBank()+regNum] != 0x00 ) {
			IR = ROM[PC++];
			PC += (char)IR;
		    }
		    else {
			PC++;
		    }
		    cycleCount += 24;
		    break;
		    
		    // DJNZ (direct), (rel)  
		case DJNZ2:
		    
		    #ifdef DEBUG
			os << "DJNZ 2" << endl;
		    #ifdef DETAIL
			os << "\t" << "RAM(" 
			   << (unsigned int)(unsigned char)ROM[PC] << ")--" << endl; 
			os << "\t" << "if( RAM(" << (unsigned int)(unsigned char)ROM[PC] 
			   << ") != 0 ) JMP " 
			   << (PC+(int)ROM[PC+1]+1) << endl;			
		    #endif
		    #endif
		    regNum = IR & 0x07;
		    IR = ROM[PC++];
		    RAM[IR < 128 ? IR : (IR+128)] = 
			(unsigned char)RAM[IR < 128 ? IR : (IR+128)] - 1;
		    if( RAM[IR < 128 ? IR : (IR+128)] != 0x00 ) {
			IR = ROM[PC++];
			PC += (char)IR;
		    }
		    else {
			PC++;
		    }
		    cycleCount += 24;
		    break;
		    
		    // MUL (A), (B)
		case MUL:
		    
		    #ifdef DEBUG
			os << "MUL" << endl;
		    #ifdef DETAIL
			os << "\t" << "A <- (A * B).(7-0)" << endl;
			os << "\t" << "B <- (A * B).(15-8)" << endl;
		    #endif
		    #endif
		    tempProduct = (unsigned char)RAM[ACC] * 
			(unsigned char)RAM[B];
		    if( tempProduct > 255 ) {
			SetBit(RAM[PSW], OV);
		    }
		    else {
			ClearBit(RAM[PSW], OV);
		    }
		    ClearBit(RAM[PSW], CY);
		    RAM[ACC] = ((unsigned char*)&tempProduct)[0];
		    RAM[B] = ((unsigned char*)&tempProduct)[1];
		    cycleCount += 48;
		    break;
		    
		    // POP (direct)
		case POP:
		    
		    #ifdef DEBUG
			os << "POP" << endl;
		    #ifdef DETAIL
			os << "\t" << "POP RAM(" 
			   << (unsigned int)(unsigned char)(ROM[PC]) << ")"
			   << endl;
		    #endif
		    #endif
		    IR = ROM[PC++];
		    RAM[IR < 128 ? IR : (IR+128)] = 
			RAM[(unsigned char)RAM[SP]--];
		    cycleCount += 24;
		    break;
		    
		    // PUSH (direct)
		case PUSH:
		    
		    #ifdef DEBUG
			os << "PUSH" << endl;
		    #ifdef DETAIL
			os << "\t" << "PUSH RAM(" 
			   << (unsigned int)(unsigned char)(ROM[PC]) << ")"
			   << endl;
		    #endif
		    #endif
		    IR = ROM[PC++];
		    RAM[(unsigned char)++RAM[SP]]  = RAM[IR < 128 ? IR : (IR+128)];
		    cycleCount += 24;
		    break;
		    
		    // JB (bit), (rel)
		case JB:
		    
		    #ifdef DEBUG
			os << "JB" << endl;
		    #ifdef DETAIL
			os << "\t" << "if( RAM(" 
			   << (int)(((ROM[PC] & 0xF8) < 128) ? 
				    (((ROM[PC] & 0xF8)>>3)+32) : (128 + (ROM[PC] & 0xF8)))
			   << ")." << (int)(ROM[PC] & 0x07) 
			   << " ) JMP " << (PC+(int)ROM[PC+1]+1)
			   << endl;
		    #endif
		    #endif
		    IR = ROM[PC++];
		    if( GetBit(RAM[((IR & 0xF8) < 128) ? 
				  (((IR & 0xF8)>>3)+32) : 
				  (128 + (IR & 0xF8))], (IR & 0x07)) == 0x01 ) {
			IR = ROM[PC++];
			PC += (char)IR;
		    }
		    else {
			PC++;
		    }
		    cycleCount += 24;
		    break;
		    
		    // JBC (bit), (rel)
		case JBC:
		    
		    #ifdef DEBUG
			os << "JB" << endl;
		    #ifdef DETAIL
			os << "if( RAM(" 
			   << (int)(((ROM[PC] & 0xF8) < 128) ? 
				    (((ROM[PC] & 0xF8)>>3)+32) : (128 + (ROM[PC] & 0xF8)))
			   << ")." << (int)(ROM[PC] & 0x07) 
			   << " )" << endl << "\t" << "{" << endl
			   << "\t\t" << "JMP " << (PC+(int)ROM[PC+1]+1)
			   << "\t\t" << "RAM(" 
			   << (int)(((ROM[PC] & 0xF8) < 128) ? 
				    (((ROM[PC] & 0xF8)>>3)+32) : (128 + (ROM[PC] & 0xF8)))
			   << ")." << (int)(ROM[PC] & 0x07) << " <- 0"
			   << "\t" << "}" << endl;
		    #endif
		    #endif
		    IR = ROM[PC++];
		    if( GetBit(RAM[((IR & 0xF8) < 128) ? 
				  (((IR & 0xF8)>>3)+32) : 
				  (128 + (IR & 0xF8))], (IR & 0x07)) == 0x01 ) {
			ClearBit(RAM[((IR & 0xF8) < 128) ? 
				    (((IR & 0xF8)>>3)+32) : 
				    (128 + (IR & 0xF8))], (IR & 0x07));
			IR = ROM[PC++];
			PC += (char)IR;
		    }
		    else {
			PC++;
		    }
		    cycleCount += 24;
		    break;
		    
		    // JC (rel)
		case JC:
		    
		    #ifdef DEBUG
			os << "JC" << endl;
		    #ifdef DETAIL
			os << "\t" << "if( C ) JMP " 
			   << (PC+(int)ROM[PC+1]+1) << endl;
		    #endif
		    #endif
		    if( GetBit(RAM[PSW], CY) == 0x01 ) {
			IR = ROM[PC++];
			PC += (char)IR;
		    }
		    else {
			PC++;
		    }
		    cycleCount += 24;
		    break;
		    
		    // JMP @A+DPTR
		case JMP:
		   
		    ((unsigned char*)&tempDPTR)[1] = RAM[DPH];
		    ((unsigned char*)&tempDPTR)[0] = RAM[DPL];
		    #ifdef DEBUG
			os << "JMP " << endl;
		    #ifdef DETAIL
			os << "JMP A + " << tempDPTR << endl;
		    #endif
		    #endif
		    tempDPTR += (unsigned char)RAM[ACC];
		    PC = (unsigned short)tempDPTR;
		    cycleCount += 24;
		    break;
		    
		    // JNB (bit), (rel)
		case JNB:
		    
		    #ifdef DEBUG
			os << "JNB" << endl;
		    #ifdef DETAIL
			os << "\t" << "if( !RAM(" 
			   << (int)(((ROM[PC] & 0xF8) < 128) ? 
				    (((ROM[PC] & 0xF8)>>3)+32) : (128 + (ROM[PC] & 0xF8)))
			   << ")." << (int)(ROM[PC] & 0x07) 
			   << " ) JMP " << (PC+(int)ROM[PC+1]+1)
			   << endl;
		    #endif
		    #endif
		    IR = ROM[PC++];
		    if( GetBit(RAM[((IR & 0xF8) < 128) ? 
				  (((IR & 0xF8)>>3)+32) : 
				  (128 + (IR & 0xF8))], (IR & 0x07)) != 0x01 ) {
			IR = ROM[PC++];
			PC += (char)IR;
		    }
		    else {
			PC++;
		    }
		    cycleCount += 24;
		    break;
		    
		    // JNC (rel)
		case JNC:
		    
		    #ifdef DEBUG
			os << "JNC" << endl;
		    #ifdef DETAIL
			os << "\t" << "if( !C ) JMP " 
			   << (PC+(int)ROM[PC+1]+1) << endl;			
		    #endif
		    #endif
		    if( GetBit(RAM[PSW], CY) == 0x00 ) {
			IR = ROM[PC++];
			PC += (char)IR;
		    }
		    else {
			PC++;
		    }
		    cycleCount += 24;
		    break;
		    
		    // JNZ (rel)
		case JNZ:
		    
		    #ifdef DEBUG
			os << "JNZ" << endl;
		    #ifdef DETAIL
			os << "\t" << "if( A != 0 ) JMP " 
			   << (PC+(int)ROM[PC+1]+1) << endl;			
		    #endif
		    #endif
		    if( RAM[ACC] != 0x00 ) {
			IR = ROM[PC++];
			PC += (char)IR;
		    }
		    else {
			PC++;
		    }
		    cycleCount += 24;
		    break;
		    
		    // JZ (rel)
		case JZ:
		    
		    #ifdef DEBUG
			os << "JZ" << endl;
		    #ifdef DETAIL
			os << "\t" << "if( A == 0 ) JMP " 
			   << (PC+(int)ROM[PC+1]+1) << endl;			
		    #endif
		    #endif
		    if( RAM[ACC] == 0x00 ) {
			IR = ROM[PC++];
			PC += (char)IR;
		    }
		    else {
			PC++;
		    }
		    cycleCount += 24;
		    break;
		    
		    // AJMP addr11
		case AJMP:
		    
		    ((unsigned char*)&jumpAddr)[1] = ((IR & 0xE0) >> 1);
		    ((unsigned char*)&jumpAddr)[0] = ROM[PC++];
		    #ifdef DEBUG
			os << "AJMP " << endl;
		    #ifdef DETAIL
			os << "\t" << "AJMP " << jumpAddr << endl;
		    #endif
		    #endif
		    PC = jumpAddr;
		    cycleCount += 24;
		    break;
		    
		    // LJMP addr16
		case LJMP:
		    
		    ((unsigned char*)&jumpAddr)[1] = ROM[PC++];
		    ((unsigned char*)&jumpAddr)[0] = ROM[PC++];
		    #ifdef DEBUG
			os << "LJMP " << endl;
		    #ifdef DETAIL
			os << "\t" << "LJMP " << jumpAddr << endl;
		    #endif
		    #endif
		    PC = jumpAddr;
		    cycleCount += 24;
		    break;
		    
		    // SJMP (rel)
		case SJMP:
		    
		    #ifdef DEBUG
			os << "SJMP " << endl;
		    #ifdef DETAIL
			os << "\t" << "SJMP " 
			   << (PC+(unsigned int)(unsigned char)ROM[PC]+1) << endl;
		    #endif
		    #endif
		    IR = ROM[PC++];
		    PC += (char)IR;
		    cycleCount += 24;
		    break;
		    
		    // A <- Rn
		case MOV1:
		    
		    #ifdef DEBUG
			os << "MOV 1" << endl;
		    #ifdef DETAIL
			os << "\t" << "A <- R" << (int)(IR & 0x07) << endl;
		    #endif
		    #endif
		    regNum = IR & 0x07;
		    RAM[ACC] = RAM[GetRegisterBank()+regNum];
		    cycleCount += 12;
		    break;
		    
		    // A <- direct
		case MOV2:
		    
		    #ifdef DEBUG
			os << "MOV 2" << endl;
		    #ifdef DETAIL
			os << "\t" << "A <- RAM(" << (unsigned int)(unsigned char)(ROM[PC]) << ")" << endl;
		    #endif
		    #endif
		    IR = ROM[PC++];
		    RAM[ACC] = RAM[IR < 128 ? IR : (IR + 128)];
		    cycleCount += 12;
		    break;
		    
		    // A <- @Ri
		case MOV3:
		    
		    #ifdef DEBUG
			os << "MOV 3" << endl;
		    #ifdef DETAIL
			os << "\t" << "A <- RAM(R" << (int)(IR & 0x01) << ")" << endl;
		    #endif
		    #endif
		    regNum = IR & 0x01;
		    RAM[ACC] = RAM[RAM[GetRegisterBank()+regNum]];
		    cycleCount += 12;
		    break;
		    
		    // A <- #data
		case MOV4:
		    
		    #ifdef DEBUG
			os << "MOV 4" << endl;
		    #ifdef DETAIL
			os << "\t" << "A <- ";
			PrintHex(ROM[PC], &os);
			os << endl;
		    #endif
		    #endif
		    IR = ROM[PC++];
		    RAM[ACC] = (char)IR;
		    cycleCount += 12;
		    break;
		    
		    // Rn <- A
		case MOV5:
		    
		    #ifdef DEBUG
			os << "MOV 5" << endl;
		    #ifdef DETAIL
			os << "\t" << "R" << (int)(IR & 0x07) << " <- A" << endl;
		    #endif
		    #endif
		    regNum = IR & 0x07;
		    RAM[GetRegisterBank()+regNum] = RAM[ACC];
		    cycleCount += 12;
		    break;
		    
		    // Rn <- direct
		case MOV6:
		    
		    #ifdef DEBUG
			os << "MOV 6" << endl;
		    #ifdef DETAIL
			os << "\t" << "R" << (int)(IR & 0x07) << " <- RAM(" 
			   << (unsigned int)(unsigned char)(ROM[PC]) << ")" << endl;
		    #endif
		    #endif
		    regNum = IR & 0x07;
		    IR = ROM[PC++];
		    RAM[GetRegisterBank()+regNum] = 
			RAM[ (IR < 128) ? IR : (IR + 128)]; 
		    cycleCount += 24;
		    break;
		    
		    // Rn <- #data
		case MOV7:
		    
		    #ifdef DEBUG
			os << "MOV 7" << endl;
		    #ifdef DETAIL
			os << "\t" << "R" << (int)(IR & 0x07) << " <- ";
			PrintHex(ROM[PC], &os);
			os << endl;
		    #endif
		    #endif
		    regNum = IR & 0x07;
		    IR = ROM[PC++];
		    RAM[GetRegisterBank()+regNum] = (char)IR;
		    cycleCount += 12;
		    break;

		    // direct <- A
		case MOV8:
		    
		    #ifdef DEBUG
			os << "MOV 8" << endl;
		    #ifdef DETAIL
			os << "\t" << "RAM(" << (unsigned int)(unsigned char)(ROM[PC]) << ") <- A" << endl;
		    #endif
		    #endif
		    IR = ROM[PC++];
		    RAM[(IR < 128) ? IR : (IR+128)] = RAM[ACC];
		    cycleCount += 12;
		    break;
		    
		    // direct <- Rn
		case MOV9:
		    
		    #ifdef DEBUG
			os << "MOV 9" << endl;
		    #ifdef DETAIL
			os << "\t" << "RAM(" << (unsigned int)(unsigned char)(ROM[PC]) << ") <- R" 
			   << (int)(IR & 0x07) << endl;
		    #endif
		    #endif
		    regNum = IR & 0x07;
		    IR = ROM[PC++];
		    RAM[(IR<128) ? IR : (IR+128)] = 
			RAM[GetRegisterBank()+regNum];
		    cycleCount += 24;
		    break;
		    
		    // direct <- direct
		case MOV10:
		    
		    #ifdef DEBUG
			os << "MOV 10" << endl;
		    #ifdef DETAIL