i8051.cc.txt

8051的IP,采用VHDL语言描述,支持intel的HEX格式,包括中断,定时器等.

		    #ifdef DETAIL
			os << "\t" << "C <- 1" << endl;
		    #endif
		    #endif
		    SetBit(RAM[PSW], CY);
		    cycleCount += 12;
		    break;
		
		    // SETB (bit)
		case SETB2:
		
		    #ifdef DEBUG
			os << "SETB 2" << endl;
		    #ifdef DETAIL
			os << "\t" << "RAM(" << (int)(((ROM[PC] & 0xF8) < 128) ? 
			    (((ROM[PC] & 0xF8)>>3)+32) : (128 + (ROM[PC] & 0xF8)))
			   << ")." << (int)(ROM[PC] & 0x07) << " <- 1" << endl;
		    #endif
		    #endif
		    IR = ROM[PC++];
		    SetBit(RAM[((IR & 0xF8) < 128) ? 
			      (((IR & 0xF8)>>3)+32) : 
			      (128 + (IR & 0xF8))], (IR & 0x07));
		    cycleCount += 12;
		    break;
		
		    // CPL (A)
		case CPL1:
		
		    #ifdef DEBUG
			os << "CPL 1" << endl;
		    #ifdef DETAIL
			os << "\t" << "A <- ~A" << endl;
		    #endif
		    #endif
		    RAM[ACC] = ~RAM[ACC];
		    cycleCount += 12;
		    break;
		
		    // CPL (C)
		case CPL2:
		
		    #ifdef DEBUG
			os << "CPL 2" << endl;
		    #ifdef DETAIL
			os << "\t" << "C <- ~C" << endl;
		    #endif
		    #endif
		    if( GetBit(RAM[PSW], CY) == 0x01 ) {
			ClearBit(RAM[PSW], CY);
		    }
		    else {
			SetBit(RAM[PSW], CY);
		    }
		    cycleCount += 12;
		    break;
		
		    // CPL (bit)
		case CPL3:
		
		    #ifdef DEBUG
			os << "CPL 3" << endl;
		    #ifdef DETAIL
			os << "\t" << "RAM(" << (int)(((ROM[PC] & 0xF8) < 128) ? 
			    (((ROM[PC] & 0xF8)>>3)+32) : (128 + (ROM[PC] & 0xF8)))
			   << ")." << (int)(ROM[PC] & 0x07) << " <- ~RAM(" 
			   << (int)(((ROM[PC] & 0xF8) < 128) ? 
				    (((ROM[PC] & 0xF8)>>3)+32) : (128 + (ROM[PC] & 0xF8)))
			   << ")." << (int)(ROM[PC] & 0x07) << endl;
		    #endif
		    #endif
		    IR = ROM[PC++];
		    if( GetBit(RAM[((IR & 0xF8) < 128) ? 
				  (((IR & 0xF8)>>3)+32) : 
				  (128 + (IR & 0xF8))], (IR & 0x07)) == 0x01 ) {
			ClearBit(RAM[((IR & 0xF8) < 128) ? 
				    (((IR & 0xF8)>>3)+32) : 
				    (128 + (IR & 0xF8))], (IR & 0x07));
		    }
		    else {
			SetBit(RAM[((IR & 0xF8) < 128) ? 
				  (((IR & 0xF8)>>3)+32) : 
				  (128 + (IR & 0xF8))], (IR & 0x07));
		    }
		    cycleCount += 12;
		    break;
		    
		    // Rotate Left (A)
		case RL:
		    
		    #ifdef DEBUG
			os << "RL" << endl;
		    #ifdef DETAIL
			os << "\t" << "RL A" << endl;
		    #endif
		    #endif
		    rotateBit = GetBit(RAM[ACC], 7);
		    RAM[ACC] = (unsigned char)RAM[ACC] << 1;
		    if( rotateBit == 0x01 ) {
			SetBit(RAM[ACC], 0);
		    }
		    else {
			ClearBit(RAM[ACC], 0);
		    }
		    cycleCount += 12;
		    break;
		    
		    // Rotate Left Thru Carry(A)
		case RLC:
		   
		    #ifdef DEBUG
			os << "RLC" << endl;
		    #ifdef DETAIL
			os << "\t" << "RLC A" << endl;
		    #endif
		    #endif
		    rotateBit = GetBit(RAM[ACC], 7);
		    RAM[ACC] = (unsigned char)RAM[ACC] << 1;		    
		    if( GetBit(RAM[PSW], CY) == 0x01 ) {
			SetBit(RAM[ACC], 0);
		    }
		    else {
			ClearBit(RAM[ACC], 0);
		    }
		    if( rotateBit == 0x01 ) {
			SetBit(RAM[PSW], CY);
		    }
		    else {
			ClearBit(RAM[PSW], CY);
		    }
		    cycleCount += 12;
		    break;
		    
		    // Rotate Right (A)
		case RR:
		    
		    #ifdef DEBUG
			os << "RR" << endl;
		    #ifdef DETAIL
			os << "\t" << "RR A" << endl;
		    #endif
		    #endif
		    rotateBit = GetBit(RAM[ACC], 0);
		    RAM[ACC] = (unsigned char)RAM[ACC] >> 1;
		    if( rotateBit == 0x01 ) {
			SetBit(RAM[ACC], 7);
		    }
		    else {
			ClearBit(RAM[ACC], 7);
		    }
		    
		    cycleCount += 12;
		    break;
		    
		    // Rotate Right Thru Carry(A)
		case RRC:
		    
		    #ifdef DEBUG
			os << "RRC" << endl;
		    #ifdef DETAIL
			os << "\t" << "RRC A" << endl;
		    #endif
		    #endif
		    rotateBit = GetBit(RAM[ACC], 0);
		    RAM[ACC] = (unsigned char)RAM[ACC] >> 1;
		    if( GetBit(RAM[PSW], CY) == 0x01 ) {
			SetBit(RAM[ACC], 7);
		    }
		    else {
			ClearBit(RAM[ACC], 7);
		    }
		    if( rotateBit == 0x01 ) {
			SetBit(RAM[PSW], CY);
		    }
		    else {
			ClearBit(RAM[PSW], CY);
		    }
		    cycleCount += 12;
		    break;
		    
		    // Swap nibbles(A)
		case SWAP:
		    
		    #ifdef DEBUG
			os << "SWAP" << endl;
		    #ifdef DETAIL
			os << "\t" << "A.(3-0) <-> A(7-4)" << endl;
		    #endif
		    #endif
		    lowerNibble = RAM[ACC] & 0x0F;
		    RAM[ACC] = RAM[ACC] >> 4;
		    RAM[ACC] |= (lowerNibble << 4);
		    cycleCount += 12;
		    break;
		    
		    // XCH (A), (Rn)
		case XCH1:
		    
		    #ifdef DEBUG
			os << "XCH 1" << endl;
		    #ifdef DETAIL
			os << "\t" << "A <-> R" << (int)(IR & 0x07) << endl;
		    #endif
		    #endif
		    regNum = IR & 0x07;
		    temp = RAM[ACC];
		    RAM[ACC] = RAM[GetRegisterBank()+regNum];
		    RAM[GetRegisterBank()+regNum] = temp;
		    cycleCount += 12;
		    break;
		    
		    // XCH (A), (direct)
		case XCH2:
		    
		    #ifdef DEBUG
			os << "XCH 2" << endl;
		    #ifdef DETAIL
			os << "\t" << "A <-> RAM(" << (unsigned int)(unsigned char)(ROM[PC]) << ")" << endl;
		    #endif
		    #endif
		    IR = ROM[PC++];
		    temp = RAM[ACC];
		    RAM[ACC] = RAM[IR < 128 ? IR : (IR+128)];
		    RAM[IR < 128 ? IR : (IR+128)] = temp;
		    cycleCount += 12;
		    break;
		    
		    // XCH (A), ((Ri))
		case XCH3:
		    
		    #ifdef DEBUG
			os << "XCH 3" << endl;
		    #ifdef DETAIL
			os << "\t" << "A <-> RAM(R" << (int)(IR & 0x01) << ")" << endl;
		    #endif
		    #endif
		    regNum = IR & 0x01;
		    temp = RAM[ACC];
		    RAM[ACC] = RAM[RAM[GetRegisterBank()+regNum]];
		    RAM[RAM[GetRegisterBank()+regNum]] = temp;
		    cycleCount += 12;
		    break;
		    
		    // XCHD (A), ((Ri))
		case XCHD:
		    
		    #ifdef DEBUG
			os << "XCHD" << endl;
		    #ifdef DETAIL
			os << "\t" << "A.(3-0) <-> RAM(R" << (int)(IR & 0x01) << ").(3-0)" << endl;
		    #endif
		    #endif
		    regNum = IR & 0x01;
		    temp = RAM[ACC] & 0x0F;
		    RAM[ACC] = (RAM[ACC] & 0xF0) | 
			(RAM[RAM[GetRegisterBank()+regNum]] & 0x0F);
		    RAM[RAM[GetRegisterBank()+regNum]] = 
			(RAM[RAM[GetRegisterBank()+regNum]] & 0xF0 ) | temp;
		    cycleCount += 12;
		    break;
		    
		    // LCALL addr16
		case LCALL:
		    
		    ((unsigned char*)&jumpAddr)[1] = ROM[PC++];
		    ((unsigned char*)&jumpAddr)[0] = ROM[PC++];
		    #ifdef DEBUG
			os << "LCALL" << endl;
		    #ifdef DETAIL
			os << "\t" << "LCALL " << jumpAddr << endl;
		    #endif
		    #endif
		    RAM[++RAM[SP]]  = ((unsigned char*)&PC)[0];
		    RAM[++RAM[SP]]  = ((unsigned char*)&PC)[1];
		    PC = jumpAddr;
		    cycleCount += 24;
		    break;
		    
		    // ACALL addr11
		case ACALL:
		  
		    ((unsigned char*)&jumpAddr)[1] = ((IR & 0xE0) >> 1);
		    ((unsigned char*)&jumpAddr)[0] = ROM[PC++];
		    #ifdef DEBUG
			os << "ACALL" << endl;
		    #ifdef DETAIL
			os << "\t" << "ACALL " << jumpAddr << endl;
		    #endif
		    #endif
		    //RAM[SP] = (unsigned char)RAM[SP] + 1;
		    RAM[++RAM[SP]]  = ((unsigned char*)&PC)[0];
		    //RAM[SP] = (unsigned char)RAM[SP] + 1;
		    RAM[++RAM[SP]]  = ((unsigned char*)&PC)[1];
		    PC = jumpAddr;
		    cycleCount += 24;
		    break;
		    
		    // DA (A)
		case DA:
		    
		    #ifdef DEBUG
			os << "DA" << endl;
		    #ifdef DETAIL
			os << "\t" << "DA A" << endl;
		    #endif
		    #endif
		    if( (RAM[ACC] & 0x0F) > 9 || 
			GetBit(RAM[PSW], AC) == 0x01 ) {
			tempAdd = RAM[ACC] + 0x06;
			RAM[ACC] = (char)tempAdd;
			if( ((unsigned char*)&tempAdd)[1] != 0 ) {
			    SetBit(RAM[PSW], CY);
			}
		    }
		    if( ((RAM[ACC] & 0x0F) >> 4) > 9 || 
			GetBit(RAM[PSW], CY) == 0x01 ) {
			tempAdd = RAM[ACC] + 0x60;
			if( ((unsigned char*)&tempAdd)[1] != 0 ) {
			    SetBit(RAM[PSW], CY);
			}
		    }
		    cycleCount += 12;
		    break;
		    
		    // CJNE (A), (direct), (rel)
		case CJNE1:
		    
		    #ifdef DEBUG
			os << "CJNE 1" << endl;
		    #ifdef DETAIL
			os << "\t" << "if( A != RAM(" << (unsigned int)(unsigned char)ROM[PC] 
			   << ") ) JMP " << (PC+(int)ROM[PC+1]+1) << endl
			   << "\t" << "if( A < RAM(" << (unsigned int)(unsigned char)ROM[PC] 
			   << ") ) C <- 1" << endl
			   << "\t" << "else C <- 0" << endl;
		    #endif
		    #endif
		    IR = ROM[PC++];
		    directAddr = IR;
		    if( RAM[ACC] != RAM[IR < 128 ? IR : (IR+128)] ) {
			IR = ROM[PC++];
			PC += (char)IR;
		    }
		    else {
			PC++;
		    }
		    if( (unsigned char)RAM[ACC] < 
			(unsigned char)RAM[directAddr < 128 ? directAddr: 
					  (directAddr+128)] ) {
			SetBit(RAM[PSW], CY);
		    }
		    else {
			ClearBit(RAM[PSW], CY);
		    }
		    cycleCount += 24;
		    break;
		    
		    // CJNE (A), (#data), (rel)
		case CJNE2:
		   
		    #ifdef DEBUG
			os << "CJNE 2" << endl;
		    #ifdef DETAIL
			os << "\t" << "if( A != ";
			PrintHex(ROM[PC], &os);
			os << " ) JMP " << (PC+(int)ROM[PC+1]+1) << endl
			   << "\t" << "if( A < ";
			PrintHex(ROM[PC], &os);
			os << " ) C <- 1" << endl
			   << "\t" << "else C <- 0" << endl;
		    #endif
		    #endif
		    IR = ROM[PC++];
		    directAddr = IR;
		    if( RAM[ACC] != (char)IR ) {
			IR = ROM[PC++];
			PC += (char)IR;
		    }
		    else {
			PC++;
		    }
		    if( (unsigned char)RAM[ACC] < (unsigned char)directAddr ) {
			SetBit(RAM[PSW], CY);
		    }
		    else {
			ClearBit(RAM[PSW], CY);
		    }
		    cycleCount += 24;
		    break;
		    
		    // CJNE (Rn), (#data), (rel)
		case CJNE3:
		    
		    #ifdef DEBUG
			os << "CJNE 3" << endl;
		    #ifdef DETAIL
			os << "\t" << "if( R" << (int)(IR & 0x07) << " != ";
			PrintHex(ROM[PC], &os);
			os << " ) JMP " << (PC+(int)ROM[PC+1]+1) << endl
			   << "\t" << "if( R" << (int)(IR & 0x07) << " < ";
			PrintHex(ROM[PC], &os);
			os << " ) C <- 1" << endl
			   << "\t" << "else C <- 0" << endl;
		    #endif
		    #endif
		    regNum = IR & 0x07;
		    IR = ROM[PC++];
		    directAddr = IR;
		    if( RAM[GetRegisterBank()+regNum] != (char)IR ) {
			IR = ROM[PC++];
			PC += (char)IR;
		    }
		    else {
			PC++;
		    }
		    if( (unsigned char)RAM[GetRegisterBank()+regNum] < 
			(unsigned char)directAddr ) {
			SetBit(RAM[PSW], CY);
		    }
		    else {
			ClearBit(RAM[PSW], CY);
		    }
		    cycleCount += 24;
		    break;
		    
		    // CJNE ((Ri)), (#data), (rel)
		case CJNE4:
		    
		    #ifdef DEBUG
			os << "CJNE 4" << endl;
		    #ifdef DETAIL
			os << "\t" << "if( RAM(R" << (int)(IR & 0x01) << ") != ";
			PrintHex(ROM[PC], &os);
			os << " ) JMP " << (PC+(int)ROM[PC+1]+1) << endl
			   << "\t" << "if( RAM(R" << (int)(IR & 0x01) << ") < ";
			PrintHex(ROM[PC], &os);
			os << " ) C <- 1" << endl
			   << "\t" << "else C <- 0" << endl;
		    #endif
		    #endif
		    regNum = IR & 0x01;
		    IR = ROM[PC++];
		    directAddr = IR;
		    if( RAM[RAM[GetRegisterBank()+regNum]] != (char)IR ) {
			IR = ROM[PC++];
			PC += (char)IR;
		    }
		    else {
			PC++;
		    }
		    
		    if( (unsigned char)RAM[RAM[GetRegisterBank()+regNum]] < 
			(unsigned char)directAddr ) {
			SetBit(RAM[PSW], CY);
		    }
		    else {
			ClearBit(RAM[PSW], CY);
		    }
		    cycleCount += 24;
		    break;
		    
		    // DEC (A)
		case DEC1:
		    
		    #ifdef DEBUG
			os << "DEC 1" << endl;
		    #ifdef DETAIL
			os << "\t" << "A--" << endl;
		    #endif
		    #endif
		    RAM[ACC]--;
		    cycleCount += 12;
		    break;
		    
		    // DEC (Rn)
		case DEC2:
		  
		    #ifdef DEBUG
			os << "DEC 2" << endl;
		    #ifdef DETAIL
			os << "\t" << "R" << (int)(IR & 0x07) << "--" << endl;
		    #endif
		    #endif
		    regNum = IR & 0x07;
		    RAM[GetRegisterBank()+regNum]--;
		    cycleCount += 12;
		    break;
		    
		    // DEC (direct)
		case DEC3:
		    
		    #ifdef DEBUG
			os << "DEC 2" << endl;
		    #ifdef DETAIL
			os << "\t" << "RAM(" << (unsigned int)(unsigned char)ROM[PC] << ")--" << endl; 
		    #endif
		    #endif
		    IR = ROM[PC++];
		    RAM[IR < 128 ? IR : (IR+128)]--;
		    cycleCount += 12;
		    break;
		    
		    // DEC ((Ri))
		case DEC4:
		    
		    #ifdef DEBUG
			os << "DEC 4" << endl;
		    #ifdef DETAIL
			os << "\t" << "RAM(R" << (int)(IR & 0x01) << ")--" << endl; 
		    #endif
		    #endif
		    regNum = IR & 0x01;
		    RAM[RAM[GetRegisterBank()+regNum]]--;
		    cycleCount += 12;
		    break;
		    
		    // DIV (A)/(B)
		case DIV:
		    
		    #ifdef DEBUG
			os << "DIV" << endl;
		    #ifdef DETAIL
			os << "\t" << "A <- A / B" << endl;
			os << "\t" << "B <- A % B" << endl;
		    #endif
		    #endif
		    if( RAM[B] == 0x00 ) {
			SetBit(RAM[PSW], OV);
		    }
		    else {
			ClearBit(RAM[PSW], OV);
			tempACC = RAM[ACC];
			RAM[ACC] = tempACC/RAM[B];
			RAM[B] = tempACC%RAM[B];
		    }		    
		    ClearBit(RAM[PSW], CY);
		    cycleCount += 48;
		    break;
		    
		    // INC (A)
		case INC1:
		    
		    #ifdef DEBUG
			os << "INC 1" << endl;
		    #ifdef DETAIL
			os << "\t" << "A++" << endl;
		    #endif
		    #endif
		    RAM[ACC]++;
		    cycleCount += 12;
		    break;
		    
		    // INC (Rn)