i8051.cc.txt

8051的IP,采用VHDL语言描述,支持intel的HEX格式,包括中断,定时器等.

//-----------------------------------------------------------------------------

// Roman Lysecky, Tony Givargis, and Greg Stitt
// Copyright 1999, All Rights Reserved.

//-----------------------------------------------------------------------------

// Version 1.3
//
// Fixed bug with ANL and XRL instructions.
// Bux fix provided by Ann Gordon-Ross.

//-----------------------------------------------------------------------------

// Version 1.2
// 
// Fixed bug with loading HEX files not generated by the Keil compiler.
// Bug fix provided by Lars Wehmeyer.

//-----------------------------------------------------------------------------

#include <iostream>
#include <iomanip>
#include <fstream>
#include <stdlib.h>
#include <stdio.h>
#include <time.h>
#include <string.h>
#include "i8051.h"

//-----------------------------------------------------------------------------

I8051::I8051() : InvalidData(11),
                 LineLength(80),
                 RecordTypeLength(3),
                 ACC(0x0160),
                 PSW(0x0150),
                 B(0x0170),
                 SP(0x0101),
                 P0(0x0100),
                 P1(0x0110),
                 P2(0x0120),
                 P3(0x0130),
                 DPL(0x0102),
                 DPH(0x0103),
                 PC(0),
                 instrCount(0),
                 cycleCount(0),
                 progEnd(false)
{
    // no code
}

//-----------------------------------------------------------------------------

I8051::~I8051() 
{
    // no code
}

//-----------------------------------------------------------------------------

bool 
I8051::Simulate(const char* inFile, const char* outFile) 
{
    ofstream os;

    clock_t begin, end;

    unsigned short tempProduct = 0;
    unsigned short jumpAddr;
    short tempAdd;
    unsigned char directAddr = 0;
    unsigned char regNum;
    unsigned char rotateBit;
    unsigned char lowerNibble;
    unsigned char tempACC;
    char temp;

    bool carry3;
    bool carry6;
    bool carry7;
    bool borrow3;
    bool borrow6;
    bool borrow7;

#ifdef PORTS
    char lastP0 = 0xFF;
    char lastP1 = 0xFF;
    char lastP2 = 0xFF;
    char lastP3 = 0xFF;
#endif
    
    if( !LoadHex(inFile) ) {
        return false;
    }
    else {
        #ifdef DEBUG
	    os.open(outFile);
	    if( os.bad() ) {
		cerr << "Error: bad output file." << endl;
		return false;
	    }
	#endif

        // initialize 8051 internal RAM
	Init8051(RAM);
	
	begin = clock();
	
	// program Loaded emulate program
	while(!progEnd) {
	    
	    if( PC >= RomSize ) PC = 0;
	    
	    #ifdef DEBUG
	    #ifdef DEBUG_PC
	        os << setw(5) << setfill('0') << PC << " - ";	       
            #endif
            #endif

	    // get instruction
	    IR = ROM[PC++];

	    // increment number of instructions executed
	    instrCount++;
	    
	    switch(Decode(IR)) {
		
		//(A) <- (A) & (Rn)
		case ANL1:
		    
		    #ifdef DEBUG
			os << "ANL 1" << endl;
		    #ifdef DETAIL
			os << "\t" << "A <- A & R" << (int)(IR & 0x07) << endl;
		    #endif
		    #endif
		    regNum = IR & 0x07;
		    RAM[ACC] &= RAM[GetRegisterBank()+regNum];
		    cycleCount += 12;
		    break;
		    
		    //(A) <- (A) & (direct)		  
		case ANL2:
		    
		    #ifdef DEBUG
			os << "ANL 2" << endl;
		    #ifdef DETAIL
			os << "\t" << "A <- A & RAM(" << (unsigned int)(unsigned char)ROM[PC] << ")" << endl;
		    #endif
		    #endif
		    IR = ROM[PC++];
		    RAM[ACC] &= RAM[IR < 128 ? IR : (IR+128)];
		    cycleCount += 12;
		    break;
		    
		    //(A) <- (A) & ((Ri))
		case ANL3:
		    
 		    #ifdef DEBUG
			os << "ANL 3" << endl;
		    #ifdef DETAIL
			os << "\t" << "A <- A & RAM(R" << (int)(IR & 0x01) << ")" << endl;
		    #endif
		    #endif
		    regNum = IR & 0x01;
		    RAM[ACC] &= RAM[RAM[GetRegisterBank()+regNum]];
		    cycleCount += 12;
		    break;
		    
		    //(A) <- (A) & (#data)
		case ANL4:
		
		    #ifdef DEBUG
			os << "ANL 4" << endl;
		    #ifdef DETAIL
			os << "\t" << "A <- A & "; PrintHex(ROM[PC], &os); os << endl;
		    #endif
		    #endif
		    IR = ROM[PC++];
		    RAM[ACC] &= (char)IR;
		    cycleCount += 12;
		    break;
		
		    // (direct) <- (direct) & (A)
		case ANL5:
		
		    #ifdef DEBUG
			os << "ANL 5" << endl;
		    #ifdef DETAIL
			os << "\t" << "RAM(" << (unsigned int)(unsigned char)ROM[PC] 
			   << ") <- RAM(" << (unsigned int)(unsigned char)ROM[PC] 
			   << " & A" << endl;
		    #endif
		    #endif
		    IR = ROM[PC++];
		    RAM[IR < 128 ? IR : (IR+128)] &= RAM[ACC];
		    cycleCount += 12;
		    break;
		
		    //(direct) <- (direct) & (#data)
		case ANL6:
		
		    #ifdef DEBUG
			os << "ANL 6" << endl;
		    #ifdef DETAIL
			os << "\t" << "RAM(" << (unsigned int)(unsigned char)ROM[PC] 
			   << ") <- RAM(" << (unsigned int)(unsigned char)ROM[PC] 
			   << " & "; 
			PrintHex(ROM[PC+1], &os); os << endl;
		    #endif
		    #endif
		    directAddr = ROM[PC++];
		    IR = ROM[PC++];
		    RAM[directAddr < 128 ? directAddr : (directAddr+128)] &= 
			IR;
		    cycleCount += 24;
		    break;

		    // (C) <- (C) & (bit)
		case ANL7:
		
		    #ifdef DEBUG
			os << "ANL 7" << endl;
		    #ifdef DETAIL
			os << "\t" << "C <- C & RAM(" 
			   << (int)(((ROM[PC] & 0xF8) < 128) ? 
			    (((ROM[PC] & 0xF8)>>3)+32) : (128 + (ROM[PC] & 0xF8)))
			   << ")." << (int)(ROM[PC] & 0x07) << endl;
		    #endif
		    #endif
		    IR = ROM[PC++];
		    if( (GetBit(RAM[PSW], CY) & 
			 GetBit(RAM[((IR & 0xF8) < 128) ? 
				   (((IR & 0xF8)>>3)+32) : 
				   (128 + (IR & 0xF8))], (IR & 0x07))) != 0x00 ) {
			SetBit(RAM[PSW], CY);
		    }
		    else {
			ClearBit(RAM[PSW], CY);
		    }
		    cycleCount += 24;
		    break;
		
		    // (C) <- (C) & /(bit)
		case ANL8:
		
		    #ifdef DEBUG
			os << "ANL 8" << endl;
		    #ifdef DETAIL
			os << "\t" << "C <- C & !RAM(" 
			   << (int)(((ROM[PC] & 0xF8) < 128) ? 
			    (((ROM[PC] & 0xF8)>>3)+32) : (128 + (ROM[PC] & 0xF8)))
			   << ")." << (int)(ROM[PC] & 0x07) << endl;
		    #endif
		    #endif
		    IR = ROM[PC++];
		    if( (GetBit(RAM[PSW], CY) & 
			 (~GetBit(RAM[((IR & 0xF8) < 128) ? 
				     (((IR & 0xF8)>>3)+32) : 
				     (128 + (IR & 0xF8))], 
				  (IR & 0x07)) & 0x01)) != 0x00 ) {
			SetBit(RAM[PSW], CY);
		    }
		    else {
			ClearBit(RAM[PSW], CY);
		    }		  
		    cycleCount += 24;
		    break;
		
		    //(A) <- (A) | (Rn)
		case ORL1:
		
		    #ifdef DEBUG
			os << "ORL 1" << endl;
		    #ifdef DETAIL
			os << "\t" << "A <- A | R" << (int)(IR & 0x07) << endl;
		    #endif
		    #endif
		    regNum = IR & 0x07;
		    RAM[ACC] |= RAM[GetRegisterBank()+regNum];
		    cycleCount += 12;
		    break;
		
		    //(A) <- (A) | (direct)		  
		case ORL2:
		
		    #ifdef DEBUG
			os << "ORL 2" << endl;
		    #ifdef DETAIL
			os << "\t" << "A <- A | RAM(" << (unsigned int)(unsigned char)ROM[PC] << ")" << endl;
		    #endif
		    #endif
		    IR = ROM[PC++];
		    RAM[ACC] |= RAM[IR < 128 ? IR : (IR+128)];
		    cycleCount += 12;
		    break;
		
		    //(A) <- (A) | ((Ri))
		case ORL3:
		
		    #ifdef DEBUG
			os << "ORL 3" << endl;
		    #ifdef DETAIL
			os << "\t" << "A <- A | RAM(R" << (int)(IR & 0x01) << ")" << endl;
		    #endif
		    #endif
		    regNum = IR & 0x01;
		    RAM[ACC] |= RAM[RAM[GetRegisterBank()+regNum]];
		    cycleCount += 12;
		    break;
		
		    //(A) <- (A) | (#data)
		case ORL4:
		
		    #ifdef DEBUG
			os << "ORL 4" << endl;
		    #ifdef DETAIL
			os << "\t" << "A <- A | "; PrintHex(ROM[PC], &os); os << endl;
		    #endif
		    #endif
		    IR = ROM[PC++];
		    RAM[ACC] |= (char)IR;
		    cycleCount += 12;
		    break;
		
		    // (direct) <- (direct) | (A)
		case ORL5:
		
		    #ifdef DEBUG
			os << "ORL 5" << endl;
		    #ifdef DETAIL
			os << "\t" << "RAM(" << (unsigned int)(unsigned char)ROM[PC] 
			   << ") <- RAM(" << (unsigned int)(unsigned char)ROM[PC] 
			   << " | A" << endl;
		    #endif
		    #endif
		    IR = ROM[PC++];
		    RAM[IR < 128 ? IR : (IR+128)] |= RAM[ACC];
		    cycleCount += 12;
		    break;
		
		    //(direct) <- (direct) | (#data)
		case ORL6:
		
		    #ifdef DEBUG
			os << "ORL 6" << endl;
		    #ifdef DETAIL
			os << "\t" << "RAM(" << (unsigned int)(unsigned char)ROM[PC] 
			   << ") <- RAM(" << (unsigned int)(unsigned char)ROM[PC] 
			   << " | "; 
			PrintHex(ROM[PC+1], &os); os << endl;
		    #endif
		    #endif
		    directAddr = ROM[PC++];
		    IR = ROM[PC++];
		    RAM[directAddr < 128 ? directAddr : (directAddr+128)]
			|= (char)IR;
		    cycleCount += 24;
		    break;
		
		    // (C) <- (C) | (bit)
		case ORL7:
		
		    #ifdef DEBUG
			os << "ORL 7" << endl;
		    #ifdef DETAIL
			os << "\t" << "C <- C | RAM(" 
			   << (int)(((ROM[PC] & 0xF8) < 128) ? 
			    (((ROM[PC] & 0xF8)>>3)+32) : (128 + (ROM[PC] & 0xF8)))
			   << ")." << (int)(ROM[PC] & 0x07) << endl;
		    #endif
		    #endif
		    IR = ROM[PC++];
		    if( (GetBit(RAM[PSW], CY) | 
			 GetBit(RAM[((IR & 0xF8) < 128) ? 
				   (((IR & 0xF8)>>3)+32) : 
				   (128 + (IR & 0xF8))], (IR & 0x07))) != 0x00 ) {
			SetBit(RAM[PSW], CY);
		    }
		    else {
			ClearBit(RAM[PSW], CY);
		    }
		    cycleCount += 24;
		    break;
		
		    // (C) <- (C) | /(bit)		  
		case ORL8:
		
		    #ifdef DEBUG
			os << "ORL 8" << endl;
		    #ifdef DETAIL
			os << "\t" << "C <- C | !RAM(" 
			   << (int)(((ROM[PC] & 0xF8) < 128) ? 
			    (((ROM[PC] & 0xF8)>>3)+32) : (128 + (ROM[PC] & 0xF8)))
			   << ")." << (int)(ROM[PC] & 0x07) << endl;
		    #endif
		    #endif
		    IR = ROM[PC++];
		    if( (GetBit(RAM[PSW], CY) | 
			 (~GetBit(RAM[((IR & 0xF8) < 128) ? 
				     (((IR & 0xF8)>>3)+32) : 
				     (128 + (IR & 0xF8))], 
				  (IR & 0x07)) & 0x01)) != 0x00 ) {
			SetBit(RAM[PSW], CY);
		    }
		    else {
			ClearBit(RAM[PSW], CY);
		    }		  
		    cycleCount += 24;
		    break;
		
		    //(A) <- (A) ^ (Rn)
		case XRL1:
		
		    #ifdef DEBUG
			os << "XRL 1" << endl;
		    #ifdef DETAIL
			os << "\t" << "A <- A ^ R" << (int)(IR & 0x07) << endl;
		    #endif
		    #endif
		    regNum = IR & 0x07;
		    RAM[ACC] ^= RAM[GetRegisterBank()+regNum];
		    cycleCount += 12;
		    break;
		
		    //(A) <- (A) ^ (direct)		  
		case XRL2:
		
		    #ifdef DEBUG
			os << "XRL 2" << endl;
		    #ifdef DETAIL
			os << "\t" << "A <- A ^ RAM(" << (unsigned int)(unsigned char)ROM[PC] << ")" << endl;
		    #endif
		    #endif
		    IR = ROM[PC++];
		    RAM[ACC] ^= RAM[IR < 128 ? IR : (IR+128)];
		    cycleCount += 12;
		    break;
		
		    //(A) <- (A) ^ ((Ri))
		case XRL3:
		
		    #ifdef DEBUG
			os << "XRL 3" << endl;
		    #ifdef DETAIL
			os << "\t" << "A <- A ^ RAM(R" << (int)(IR & 0x01) << ")" << endl;
		    #endif
		    #endif
		    regNum = IR & 0x01;
		    RAM[ACC] ^= RAM[RAM[GetRegisterBank()+regNum]];
		    cycleCount += 12;
		    break;
		
		    //(A) <- (A) ^ (#data)
		case XRL4:
		
		    #ifdef DEBUG
			os << "XRL 4" << endl;
		    #ifdef DETAIL
			os << "\t" << "A <- A ^ "; PrintHex(ROM[PC], &os); os << endl;
		    #endif
		    #endif
		    IR = ROM[PC++];
		    RAM[ACC] ^= IR;
		    cycleCount += 12;
		    break;
		
		    // (direct) <- (direct) ^ (A)
		case XRL5:
		
		    #ifdef DEBUG
			os << "XRL 5" << endl;
		    #ifdef DETAIL
			os << "\t" << "RAM(" << (unsigned int)(unsigned char)ROM[PC] 
			   << ") <- RAM(" << (unsigned int)(unsigned char)ROM[PC] 
			   << " ^ A" << endl;
		    #endif
		    #endif
		    IR = ROM[PC++];
		    RAM[IR < 128 ? IR : (IR+128)] ^= RAM[ACC];
		    cycleCount += 12;
		    break;
		
		    //(direct) <- (direct) ^ (#data)
		case XRL6:
		
		    #ifdef DEBUG
			os << "XRL 6" << endl;
		    #ifdef DETAIL
			os << "\t" << "RAM(" << (unsigned int)(unsigned char)ROM[PC] 
			   << ") <- RAM(" << (unsigned int)(unsigned char)ROM[PC] 
			   << " ^ "; 
			PrintHex(ROM[PC+1], &os); os << endl;
		    #endif
		    #endif
		    directAddr = ROM[PC++];
		    IR = ROM[PC++];
		    RAM[directAddr < 128 ? directAddr : (directAddr+128)] 
			^= (char)IR;
		    cycleCount += 24;
		    break;
		
		    // CLR (A)
		case CLR1:
		
		    #ifdef DEBUG
			os << "CLR 1" << endl;
		    #ifdef DETAIL
			os << "\t" << "A <- 0x00" << endl;
		    #endif
		    #endif
		    RAM[ACC] = 0x00;
		    cycleCount += 12;
		    break;
		
		    // CLR (C)
		case CLR2:
		
		    #ifdef DEBUG
			os << "CLR 2" << endl;
		    #ifdef DETAIL
			os << "\t" << "C <- 0" << endl;
		    #endif
		    #endif
		    ClearBit(RAM[PSW], CY);
		    cycleCount += 12;
		    break;
		
		    // CLR (bit)
		case CLR3:
		
		    #ifdef DEBUG
			os << "CLR 3" << endl;
		    #endif
		    #ifdef DETAIL
			os << "\t" << "RAM(" << (int)(((ROM[PC] & 0xF8) < 128) ? 
			    (((ROM[PC] & 0xF8)>>3)+32) : (128 + (ROM[PC] & 0xF8)))
			   << ")." << (int)(ROM[PC] & 0x07) << " <- 0" << endl;
		    #endif
		    IR = ROM[PC++];
		    ClearBit(RAM[((IR & 0xF8) < 128) ? 
				(((IR & 0xF8)>>3)+32) : 
				(128 + (IR & 0xF8))], (IR & 0x07));
		    cycleCount += 12;
		    break;
		
		    // SETB (C)
		case SETB1:
		
		    #ifdef DEBUG
			os << "SETB 1" << endl;