📄 synthesizeable vhdl model of 8051.htm
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<TD><IMG src="Synthesizeable VHDL Model of 8051.files/getdomain.jpeg">
<TD><A href="http://www.cs.ucr.edu/~dalton">Dalton
Project</A><BR>University of California<BR>Dept. of Computer
Science<BR>Riverside, CA 92521<BR><A
href="mailto:dalton@cs.ucr.edu">dalton@cs.ucr.edu</A> </TD></TR></TBODY></TABLE>
<H1>Synthesizable VHDL Model of 8051</H1>The Intel 8051 is an 8-bit
micro-controller. This micro-controller is capable of addressing 64K of program
and 64K of data memory. The implementation below is written in Synthesizable
VHDL (at least by Synopsys and Xilinx,) and models the actual Intel
implementation rather closely, e.g., it is 100% instruction compatible. Visit
this page for latest information and upgrades, and keep in mind that we tend to
make frequent revisions. Do not hesitate to contact us regarding questions or
comments.<U><B><I> Needless to say, we do not, nor does the University of
California at Riverside, provide any kind of warrantee for anything you read or
download from this page.</U></B></I>
<H1>Block Diagram</H1>
<CENTER>
<TABLE border=5>
<TBODY>
<TR>
<TD><IMG
src="Synthesizeable VHDL Model of 8051.files/blkdiag.gif"></TD></TR></TBODY></TABLE></CENTER>
<H1>Limitations</H1>
<UL>
<LI>This implementation is <B>not cycle/timing</B> compatible.<BR>
<LI><B>Interrupt handling</B> is <B>not</B> currently implemented.<BR>
<LI><B>Peripheral devices</B> are <B>not</B> currently
implemented.<BR></LI></UL>We plan on, slowly, removing all the above
limitations/shortcomings. We would also appreciate any help from people willing
to contribute to this design. Please contact us.
<H1>FPGA Implemenation</H1>We are in process of testing our 8051 model on an
actual FPGA board. Our plans are to use a XILINX V300PQ240 Virtex FPGA. We will
add our test results, procedures along with other related material to this web
page. <A
href="http://www.cs.ucr.edu/~dalton/i8051/i8051syn/v300PQ240-4.txt">Here</A> is
the post synthesis report that gives FPGA cell usage as well as some timing
information. Note that about 1/2 of the FPGA is used by the RAM modules. You can
fit the design in smaller FPGA's by reducing the internal memory space. Also,
note that the maximum FPGA clock speed is 11.6 MHz!
<H1>Source File Description</H1>Here is a short description of the related
files.
<TABLE border=5 width="100%">
<TBODY>
<TR>
<TD>
<CENTER><B>File</B></CENTER></TD>
<TD>
<CENTER><B>Description</B></CENTER></TD></TR>
<TR>
<TD><A
href="http://www.cs.ucr.edu/~dalton/i8051/i8051syn/source/i8051_lib.vhd">i8051_lib.vhd</A></TD>
<TD>Defines a package that is used in all the VHDL files of the 8051
model. This package defines commonly used constants.</TD></TR>
<TR>
<TD><A
href="http://www.cs.ucr.edu/~dalton/i8051/i8051syn/source/i8051_alu.vhd">i8051_alu.vhd</A></TD>
<TD>Model of an ALU that performs 8051 specific arithmetic. This model is
described behaviorally as a combinational logic block.</TD></TR>
<TR>
<TD><A
href="http://www.cs.ucr.edu/~dalton/i8051/i8051syn/source/i8051_dec.vhd">i8051_dec.vhd</A></TD>
<TD>Model of a decoder that decodes the non-uniform 8051 instructions into
uniform representations, i.e., enumerated codes. This model is described
as a data-flow implementing a combinational logic block.</TD></TR>
<TR>
<TD><A
href="http://www.cs.ucr.edu/~dalton/i8051/i8051syn/source/i8051_ram.vhd">i8051_ram.vhd</A></TD>
<TD>Model of 128 bytes of RAM, specific to 8051, e.g., bit-addressable.
This model is described behaviorally as a sequential logic block.</TD></TR>
<TR>
<TD><A
href="http://www.cs.ucr.edu/~dalton/i8051/i8051syn/source/i8051_rom.vhd">i8051_rom.vhd*</A></TD>
<TD>Model of up to 64K bytes of ROM, specific to 8051. This model is
automatically generated behaviorally, as a sequential logic block, using
<B>i8051_mkr.c</B>.</TD></TR>
<TR>
<TD><A
href="http://www.cs.ucr.edu/~dalton/i8051/i8051syn/source/i8051_ctr.vhd">i8051_ctr.vhd</A></TD>
<TD>Model of the core 8051 processor. This model is described behaviorally
as a sequential logic block.</TD></TR>
<TR>
<TD><A
href="http://www.cs.ucr.edu/~dalton/i8051/i8051syn/source/i8051_dbg.vhd">i8051_dbg.vhd</A></TD>
<TD>This entity is there for debugging only. Currently, it outputs a trace
of each instruction that is executed.</TD></TR>
<TR>
<TD><A
href="http://www.cs.ucr.edu/~dalton/i8051/i8051syn/source/i8051_all.vhd">i8051_all.vhd</A></TD>
<TD>Model of a complete 8051 micro-controller. This model structurally
combines the above logic blocks.</TD></TR>
<TR>
<TD><A
href="http://www.cs.ucr.edu/~dalton/i8051/i8051syn/source/i8051_xrm.vhd">i8051_xrm.vhd</A></TD>
<TD>Model of external SRAM that will interface to this 8051
micro-controller. </TD>
<TR>
<TD><A
href="http://www.cs.ucr.edu/~dalton/i8051/i8051syn/source/i8051_tsb.vhd">i8051_tsb.vhd</A></TD>
<TD>Model of a test-bench for the 8051 micro-controller. This model is
described behaviorally as an I/O-less sequential logic block. (It merely
resets, then clocks the micro-controller for ever.) </TD>
<TR>
<TD><A
href="http://www.cs.ucr.edu/~dalton/i8051/i8051syn/source/i8051_mkr.c">i8051_mkr.c</A></TD>
<TD>Program to convert an Intel 8051 HEX file into a ROM model, i.e.,
generates <B>i8051_rom.vhd</B>. You will need to compile this C/C++ file,
say, <B>gcc -Wall i8051_mkr.c</B>, then run it with your HEX file as a
command line argument to it, e.g., <B>a.out myfile.hex</B>.</TD></TR>
<TR>
<TD><A
href="http://www.cs.ucr.edu/~dalton/i8051/i8051syn/source/syn_alu.inc">syn_alu.inc,</A>
<A
href="http://www.cs.ucr.edu/~dalton/i8051/i8051syn/source/syn_dec.inc">syn_dec.inc,</A>
<A
href="http://www.cs.ucr.edu/~dalton/i8051/i8051syn/source/syn_ram.inc">syn_ram.inc,</A>
<A
href="http://www.cs.ucr.edu/~dalton/i8051/i8051syn/source/syn_rom.inc">syn_rom.inc,</A>
<A
href="http://www.cs.ucr.edu/~dalton/i8051/i8051syn/source/syn_ctr.inc">syn_ctr.inc
</A></TD>
<TD>Include files, specific to <B>dc_shell</B>, that will synthesize the
above VHDL models down to gate.</TD></TR>
<TR>
<TD><A
href="http://www.cs.ucr.edu/~dalton/i8051/i8051syn/source/zsim.scr">zsim.scr,</A>
<A
href="http://www.cs.ucr.edu/~dalton/i8051/i8051syn/source/zsyn.scr">zsyn.scr</A></TD>
<TD>Script files that simulate/synthesize
everything.</TD></TR></TBODY></TABLE><I>* Up to 4K ROM model of <B>sort.c</B>
program.</I><BR>
<H1>Statistics</H1>Here is some statistics that you may find interesting. These
are obtained by synthesizing the models down to gate, using medium mapping
effort. Library binding is to <B>lsi_10k</B>, supplied by Synopsys. No
area/delay constraints have been specified. Machine in use has dual 200 MHz
Ultra Sparc II processors.
<TABLE border=5 width="100%">
<TBODY>
<TR>
<TD>
<CENTER><B>Model</B></CENTER></TD>
<TD>
<CENTER><B>I/O Ports (bit)</B></CENTER></TD>
<TD>
<CENTER><B>Combinational Area (nand-gate)</B></CENTER></TD>
<TD>
<CENTER><B>Sequential Area (nand-gate)</B></CENTER></TD>
<TD>
<CENTER><B>Critical Path Length (ns)</B></CENTER></TD>
<TD>
<CENTER><B>Maximum Clock Speed (MHz)</B></CENTER></TD>
<TD>
<CENTER><B>Synth. Time (min)</B></CENTER></TD></TR>
<TR>
<TD>I8051_ALU</TD>
<TD>
<DIV align=right>50</DIV></TD>
<TD>
<DIV align=right>2191</DIV></TD>
<TD>
<DIV align=right>0</DIV></TD>
<TD>
<DIV align=right>178</DIV></TD>
<TD>
<DIV align=right>5.63</DIV></TD>
<TD>
<DIV align=right>3</DIV></TD></TR>
<TR>
<TD>I8051_DEC</TD>
<TD>
<DIV align=right>18</DIV></TD>
<TD>
<DIV align=right>590</DIV></TD>
<TD>
<DIV align=right>0</DIV></TD>
<TD>
<DIV align=right>46.3</DIV></TD>
<TD>
<DIV align=right>21.6</DIV></TD>
<TD>
<DIV align=right>2</DIV></TD></TR>
<TR>
<TD>I8051_RAM</TD>
<TD>
<DIV align=right>31</DIV></TD>
<TD>
<DIV align=right>5237</DIV></TD>
<TD>
<DIV align=right>8663</DIV></TD>
<TD>
<DIV align=right>1.41</DIV></TD>
<TD>
<DIV align=right>709</DIV></TD>
<TD>
<DIV align=right>28</DIV></TD></TR>
<TR>
<TD>I8051_ROM*</TD>
<TD>
<DIV align=right>23</DIV></TD>
<TD>
<DIV align=right>1050</DIV></TD>
<TD>
<DIV align=right>56</DIV></TD>
<TD>
<DIV align=right>1.40</DIV></TD>
<TD>
<DIV align=right>714</DIV></TD>
<TD>
<DIV align=right>15</DIV></TD></TR>
<TR>
<TD>I8051_CTR</TD>
<TD>
<DIV align=right>118</DIV></TD>
<TD>
<DIV align=right>2202</DIV></TD>
<TD>
<DIV align=right>998</DIV></TD>
<TD>
<DIV align=right>1.77</DIV></TD>
<TD>
<DIV align=right>565</DIV></TD>
<TD>
<DIV align=right>17</DIV></TD></TR></TBODY></TABLE><I>* Up to 4K ROM model of
<B>sort.c</B> program.</I><BR><A name=test></A>
<H1>Test Files</H1>This is a collection of test-files, in C format. Our test
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