fre.vhd

基于FPGA的UART实现 用VHDL编程

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity fre is
	GENERIC (N:integer:=156);
    Port (clk:in std_logic;
	     bclk:out std_logic);
end fre;
architecture Behavioral of fre is
signal count:integer:=0;
begin
process(clk)
begin
	if(clk'event and clk='1') then
	if(count=N-1)then
		count<=0;
	else
		count<=count+1;
		if count<N/2 then
			bclk<='0';
		else
			bclk<='1';
		end if;
	end if;
	end if;
end process;
end Behavioral;