📄 uart.map.qmsg

📁 基于FPGA的UART实现用VHDL编程
💻 QMSG
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{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.0 Build 33 02/05/2007 SJ Full Version " "Info: Version 7.0 Build 33 02/05/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Aug 10 08:19:55 2007 " "Info: Processing started: Fri Aug 10 08:19:55 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off UART -c UART " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off UART -c UART" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "rxd.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file rxd.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 rxd-Behavioral " "Info: Found design unit 1: rxd-Behavioral" {  } { { "rxd.vhd" "" { Text "E:/毕设资料/程序/仿真/UART/rxd.vhd" 13 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 rxd " "Info: Found entity 1: rxd" {  } { { "rxd.vhd" "" { Text "E:/毕设资料/程序/仿真/UART/rxd.vhd" 6 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "txd.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file txd.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 txd-Behavioral " "Info: Found design unit 1: txd-Behavioral" {  } { { "txd.vhd" "" { Text "E:/毕设资料/程序/仿真/UART/txd.vhd" 13 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 txd " "Info: Found entity 1: txd" {  } { { "txd.vhd" "" { Text "E:/毕设资料/程序/仿真/UART/txd.vhd" 6 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "fre.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file fre.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 fre-Behavioral " "Info: Found design unit 1: fre-Behavioral" {  } { { "fre.vhd" "" { Text "E:/毕设资料/程序/仿真/UART/fre.vhd" 10 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 fre " "Info: Found entity 1: fre" {  } { { "fre.vhd" "" { Text "E:/毕设资料/程序/仿真/UART/fre.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "UART.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file UART.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 UART " "Info: Found entity 1: UART" {  } { { "UART.bdf" "" { Schematic "E:/毕设资料/程序/仿真/UART/UART.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "UART " "Info: Elaborating entity \"UART\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "txd txd:inst1 " "Info: Elaborating entity \"txd\" for hierarchy \"txd:inst1\"" {  } { { "UART.bdf" "inst1" { Schematic "E:/毕设资料/程序/仿真/UART/UART.bdf" { { -48 328 456 80 "inst1" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "fre fre:inst4 " "Info: Elaborating entity \"fre\" for hierarchy \"fre:inst4\"" {  } { { "UART.bdf" "inst4" { Schematic "E:/毕设资料/程序/仿真/UART/UART.bdf" { { 112 48 144 208 "inst4" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "rxd rxd:inst " "Info: Elaborating entity \"rxd\" for hierarchy \"rxd:inst\"" {  } { { "UART.bdf" "inst" { Schematic "E:/毕设资料/程序/仿真/UART/UART.bdf" { { -32 160 288 64 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT_NO_BITS" "\|UART\|rxd:inst\|state 5 " "Info: State machine \"\|UART\|rxd:inst\|state\" contains 5 states" {  } { { "rxd.vhd" "" { Text "E:/毕设资料/程序/仿真/UART/rxd.vhd" 15 -1 0 } }  } 0 0 "State machine \"%1!s!\" contains %2!d! states" 0 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT_NO_BITS" "\|UART\|txd:inst1\|state 5 " "Info: State machine \"\|UART\|txd:inst1\|state\" contains 5 states" {  } { { "txd.vhd" "" { Text "E:/毕设资料/程序/仿真/UART/txd.vhd" 15 -1 0 } }  } 0 0 "State machine \"%1!s!\" contains %2!d! states" 0 0}
{ "Info" "IOPT_SMP_MACHINE_REPORT_PROCESSOR" "Auto \|UART\|rxd:inst\|state " "Info: Selected Auto state machine encoding method for state machine \"\|UART\|rxd:inst\|state\"" {  } { { "rxd.vhd" "" { Text "E:/毕设资料/程序/仿真/UART/rxd.vhd" 15 -1 0 } }  } 0 0 "Selected %1!s! state machine encoding method for state machine \"%2!s!\"" 0 0}
{ "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_HEADER" "\|UART\|rxd:inst\|state " "Info: Encoding result for state machine \"\|UART\|rxd:inst\|state\"" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS_HEADER" "5 " "Info: Completed encoding using 5 state bits" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "rxd:inst\|state.r_stop " "Info: Encoded state bit \"rxd:inst\|state.r_stop\"" {  } { { "rxd.vhd" "" { Text "E:/毕设资料/程序/仿真/UART/rxd.vhd" 15 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "rxd:inst\|state.r_sample " "Info: Encoded state bit \"rxd:inst\|state.r_sample\"" {  } { { "rxd.vhd" "" { Text "E:/毕设资料/程序/仿真/UART/rxd.vhd" 15 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "rxd:inst\|state.r_wait " "Info: Encoded state bit \"rxd:inst\|state.r_wait\"" {  } { { "rxd.vhd" "" { Text "E:/毕设资料/程序/仿真/UART/rxd.vhd" 15 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "rxd:inst\|state.r_center " "Info: Encoded state bit \"rxd:inst\|state.r_center\"" {  } { { "rxd.vhd" "" { Text "E:/毕设资料/程序/仿真/UART/rxd.vhd" 15 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "rxd:inst\|state.r_start " "Info: Encoded state bit \"rxd:inst\|state.r_start\"" {  } { { "rxd.vhd" "" { Text "E:/毕设资料/程序/仿真/UART/rxd.vhd" 15 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0}  } {  } 0 0 "Completed encoding using %1!d! state bits" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|UART\|rxd:inst\|state.r_start 00000 " "Info: State \"\|UART\|rxd:inst\|state.r_start\" uses code string \"00000\"" {  } { { "rxd.vhd" "" { Text "E:/毕设资料/程序/仿真/UART/rxd.vhd" 15 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|UART\|rxd:inst\|state.r_center 00011 " "Info: State \"\|UART\|rxd:inst\|state.r_center\" uses code string \"00011\"" {  } { { "rxd.vhd" "" { Text "E:/毕设资料/程序/仿真/UART/rxd.vhd" 15 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|UART\|rxd:inst\|state.r_wait 00101 " "Info: State \"\|UART\|rxd:inst\|state.r_wait\" uses code string \"00101\"" {  } { { "rxd.vhd" "" { Text "E:/毕设资料/程序/仿真/UART/rxd.vhd" 15 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|UART\|rxd:inst\|state.r_sample 01001 " "Info: State \"\|UART\|rxd:inst\|state.r_sample\" uses code string \"01001\"" {  } { { "rxd.vhd" "" { Text "E:/毕设资料/程序/仿真/UART/rxd.vhd" 15 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|UART\|rxd:inst\|state.r_stop 10001 " "Info: State \"\|UART\|rxd:inst\|state.r_stop\" uses code string \"10001\"" {  } { { "rxd.vhd" "" { Text "E:/毕设资料/程序/仿真/UART/rxd.vhd" 15 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0}  } { { "rxd.vhd" "" { Text "E:/毕设资料/程序/仿真/UART/rxd.vhd" 15 -1 0 } }  } 0 0 "Encoding result for state machine \"%1!s!\"" 0 0}
{ "Info" "IOPT_SMP_MACHINE_REPORT_PROCESSOR" "Auto \|UART\|txd:inst1\|state " "Info: Selected Auto state machine encoding method for state machine \"\|UART\|txd:inst1\|state\"" {  } { { "txd.vhd" "" { Text "E:/毕设资料/程序/仿真/UART/txd.vhd" 15 -1 0 } }  } 0 0 "Selected %1!s! state machine encoding method for state machine \"%2!s!\"" 0 0}
{ "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_HEADER" "\|UART\|txd:inst1\|state " "Info: Encoding result for state machine \"\|UART\|txd:inst1\|state\"" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS_HEADER" "5 " "Info: Completed encoding using 5 state bits" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "txd:inst1\|state.x_stop " "Info: Encoded state bit \"txd:inst1\|state.x_stop\"" {  } { { "txd.vhd" "" { Text "E:/毕设资料/程序/仿真/UART/txd.vhd" 15 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "txd:inst1\|state.x_shift " "Info: Encoded state bit \"txd:inst1\|state.x_shift\"" {  } { { "txd.vhd" "" { Text "E:/毕设资料/程序/仿真/UART/txd.vhd" 15 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "txd:inst1\|state.x_wait " "Info: Encoded state bit \"txd:inst1\|state.x_wait\"" {  } { { "txd.vhd" "" { Text "E:/毕设资料/程序/仿真/UART/txd.vhd" 15 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "txd:inst1\|state.x_start " "Info: Encoded state bit \"txd:inst1\|state.x_start\"" {  } { { "txd.vhd" "" { Text "E:/毕设资料/程序/仿真/UART/txd.vhd" 15 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "txd:inst1\|state.x_idle " "Info: Encoded state bit \"txd:inst1\|state.x_idle\"" {  } { { "txd.vhd" "" { Text "E:/毕设资料/程序/仿真/UART/txd.vhd" 15 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0}  } {  } 0 0 "Completed encoding using %1!d! state bits" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|UART\|txd:inst1\|state.x_idle 00000 " "Info: State \"\|UART\|txd:inst1\|state.x_idle\" uses code string \"00000\"" {  } { { "txd.vhd" "" { Text "E:/毕设资料/程序/仿真/UART/txd.vhd" 15 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|UART\|txd:inst1\|state.x_start 00011 " "Info: State \"\|UART\|txd:inst1\|state.x_start\" uses code string \"00011\"" {  } { { "txd.vhd" "" { Text "E:/毕设资料/程序/仿真/UART/txd.vhd" 15 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|UART\|txd:inst1\|state.x_wait 00101 " "Info: State \"\|UART\|txd:inst1\|state.x_wait\" uses code string \"00101\"" {  } { { "txd.vhd" "" { Text "E:/毕设资料/程序/仿真/UART/txd.vhd" 15 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|UART\|txd:inst1\|state.x_shift 01001 " "Info: State \"\|UART\|txd:inst1\|state.x_shift\" uses code string \"01001\"" {  } { { "txd.vhd" "" { Text "E:/毕设资料/程序/仿真/UART/txd.vhd" 15 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|UART\|txd:inst1\|state.x_stop 10001 " "Info: State \"\|UART\|txd:inst1\|state.x_stop\" uses code string \"10001\"" {  } { { "txd.vhd" "" { Text "E:/毕设资料/程序/仿真/UART/txd.vhd" 15 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0}  } { { "txd.vhd" "" { Text "E:/毕设资料/程序/仿真/UART/txd.vhd" 15 -1 0 } }  } 0 0 "Encoding result for state machine \"%1!s!\"" 0 0}
{ "Info" "IFTM_FTM_PRESET_POWER_UP" "" "Info: Registers with preset signals will power-up high" {  } { { "txd.vhd" "" { Text "E:/毕设资料/程序/仿真/UART/txd.vhd" 22 -1 0 } }  } 0 0 "Registers with preset signals will power-up high" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "241 " "Info: Implemented 241 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "3 " "Info: Implemented 3 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "1 " "Info: Implemented 1 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "237 " "Info: Implemented 237 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "140 " "Info: Allocated 140 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Fri Aug 10 08:20:01 2007 " "Info: Processing ended: Fri Aug 10 08:20:01 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Info: Elapsed time: 00:00:06" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}
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