uart.hier_info

基于FPGA的UART实现 用VHDL编程

|UART
txd <= txd:inst1.txd
clk => fre:inst4.clk
reset => txd:inst1.resett
reset => rxd:inst.resetr
rxd => rxd:inst.rxdr


|UART|txd:inst1
bclkt => xbitcnt[0].CLK
bclkt => xbitcnt[1].CLK
bclkt => xbitcnt[2].CLK
bclkt => xbitcnt[3].CLK
bclkt => xbitcnt[4].CLK
bclkt => xbitcnt[5].CLK
bclkt => xbitcnt[6].CLK
bclkt => xbitcnt[7].CLK
bclkt => xbitcnt[8].CLK
bclkt => xbitcnt[9].CLK
bclkt => xbitcnt[10].CLK
bclkt => xbitcnt[11].CLK
bclkt => xbitcnt[12].CLK
bclkt => xbitcnt[13].CLK
bclkt => xbitcnt[14].CLK
bclkt => xbitcnt[15].CLK
bclkt => xbitcnt[16].CLK
bclkt => xbitcnt[17].CLK
bclkt => xbitcnt[18].CLK
bclkt => xbitcnt[19].CLK
bclkt => xbitcnt[20].CLK
bclkt => xbitcnt[21].CLK
bclkt => xbitcnt[22].CLK
bclkt => xbitcnt[23].CLK
bclkt => xbitcnt[24].CLK
bclkt => xbitcnt[25].CLK
bclkt => xbitcnt[26].CLK
bclkt => xbitcnt[27].CLK
bclkt => xbitcnt[28].CLK
bclkt => xbitcnt[29].CLK
bclkt => xbitcnt[30].CLK
bclkt => xbitcnt[31].CLK
bclkt => xcnt16[0].CLK
bclkt => xcnt16[1].CLK
bclkt => xcnt16[2].CLK
bclkt => xcnt16[3].CLK
bclkt => xcnt16[4].CLK
bclkt => txds.CLK
bclkt => state~6.IN1
resett => txds.PRESET
resett => xbitcnt[0].ENA
resett => xbitcnt[1].ENA
resett => xbitcnt[2].ENA
resett => xbitcnt[3].ENA
resett => xbitcnt[4].ENA
resett => xbitcnt[5].ENA
resett => xbitcnt[6].ENA
resett => xbitcnt[7].ENA
resett => xbitcnt[8].ENA
resett => xbitcnt[9].ENA
resett => xbitcnt[10].ENA
resett => xbitcnt[11].ENA
resett => xbitcnt[12].ENA
resett => xbitcnt[13].ENA
resett => xbitcnt[14].ENA
resett => xbitcnt[15].ENA
resett => xbitcnt[16].ENA
resett => xbitcnt[17].ENA
resett => xbitcnt[18].ENA
resett => xbitcnt[19].ENA
resett => xbitcnt[20].ENA
resett => xbitcnt[21].ENA
resett => xbitcnt[22].ENA
resett => xbitcnt[23].ENA
resett => xbitcnt[24].ENA
resett => xbitcnt[25].ENA
resett => xbitcnt[26].ENA
resett => xbitcnt[27].ENA
resett => xbitcnt[28].ENA
resett => xbitcnt[29].ENA
resett => xbitcnt[30].ENA
resett => xbitcnt[31].ENA
resett => xcnt16[0].ENA
resett => xcnt16[1].ENA
resett => xcnt16[2].ENA
resett => xcnt16[3].ENA
resett => xcnt16[4].ENA
resett => state~7.IN1
xmit_cmd_p => state~3.DATAB
xmit_cmd_p => Selector1.IN3
xmit_cmd_p => Selector0.IN1
xmit_cmd_p => state~2.DATAB
txdbuf[0] => Mux0.IN7
txdbuf[1] => Mux0.IN6
txdbuf[2] => Mux0.IN5
txdbuf[3] => Mux0.IN4
txdbuf[4] => Mux0.IN3
txdbuf[5] => Mux0.IN2
txdbuf[6] => Mux0.IN1
txdbuf[7] => Mux0.IN0
txd <= txds.DB_MAX_OUTPUT_PORT_TYPE


|UART|fre:inst4
clk => bclk~reg0.CLK
clk => count[0].CLK
clk => count[1].CLK
clk => count[2].CLK
clk => count[3].CLK
clk => count[4].CLK
clk => count[5].CLK
clk => count[6].CLK
clk => count[7].CLK
clk => count[8].CLK
clk => count[9].CLK
clk => count[10].CLK
clk => count[11].CLK
clk => count[12].CLK
clk => count[13].CLK
clk => count[14].CLK
clk => count[15].CLK
clk => count[16].CLK
clk => count[17].CLK
clk => count[18].CLK
clk => count[19].CLK
clk => count[20].CLK
clk => count[21].CLK
clk => count[22].CLK
clk => count[23].CLK
clk => count[24].CLK
clk => count[25].CLK
clk => count[26].CLK
clk => count[27].CLK
clk => count[28].CLK
clk => count[29].CLK
clk => count[30].CLK
clk => count[31].CLK
bclk <= bclk~reg0.DB_MAX_OUTPUT_PORT_TYPE


|UART|rxd:inst
bclkr => rbuf[0]~reg0.CLK
bclkr => rbuf[1]~reg0.CLK
bclkr => rbuf[2]~reg0.CLK
bclkr => rbuf[3]~reg0.CLK
bclkr => rbuf[4]~reg0.CLK
bclkr => rbuf[5]~reg0.CLK
bclkr => rbuf[6]~reg0.CLK
bclkr => rbuf[7]~reg0.CLK
bclkr => r_ready~reg0.CLK
bclkr => \pro2:rbufs[0].CLK
bclkr => \pro2:rbufs[1].CLK
bclkr => \pro2:rbufs[2].CLK
bclkr => \pro2:rbufs[3].CLK
bclkr => \pro2:rbufs[4].CLK
bclkr => \pro2:rbufs[5].CLK
bclkr => \pro2:rbufs[6].CLK
bclkr => \pro2:rbufs[7].CLK
bclkr => \pro2:rcnt[0].CLK
bclkr => \pro2:rcnt[1].CLK
bclkr => \pro2:rcnt[2].CLK
bclkr => \pro2:rcnt[3].CLK
bclkr => \pro2:rcnt[4].CLK
bclkr => \pro2:rcnt[5].CLK
bclkr => \pro2:rcnt[6].CLK
bclkr => \pro2:rcnt[7].CLK
bclkr => \pro2:rcnt[8].CLK
bclkr => \pro2:rcnt[9].CLK
bclkr => \pro2:rcnt[10].CLK
bclkr => \pro2:rcnt[11].CLK
bclkr => \pro2:rcnt[12].CLK
bclkr => \pro2:rcnt[13].CLK
bclkr => \pro2:rcnt[14].CLK
bclkr => \pro2:rcnt[15].CLK
bclkr => \pro2:rcnt[16].CLK
bclkr => \pro2:rcnt[17].CLK
bclkr => \pro2:rcnt[18].CLK
bclkr => \pro2:rcnt[19].CLK
bclkr => \pro2:rcnt[20].CLK
bclkr => \pro2:rcnt[21].CLK
bclkr => \pro2:rcnt[22].CLK
bclkr => \pro2:rcnt[23].CLK
bclkr => \pro2:rcnt[24].CLK
bclkr => \pro2:rcnt[25].CLK
bclkr => \pro2:rcnt[26].CLK
bclkr => \pro2:rcnt[27].CLK
bclkr => \pro2:rcnt[28].CLK
bclkr => \pro2:rcnt[29].CLK
bclkr => \pro2:rcnt[30].CLK
bclkr => \pro2:rcnt[31].CLK
bclkr => \pro2:count[0].CLK
bclkr => \pro2:count[1].CLK
bclkr => \pro2:count[2].CLK
bclkr => \pro2:count[3].CLK
bclkr => state~8.IN1
resetr => \pro2:count[0].ACLR
resetr => \pro2:count[1].ACLR
resetr => \pro2:count[2].ACLR
resetr => \pro2:count[3].ACLR
resetr => rbuf[2]~reg0.ENA
resetr => rbuf[1]~reg0.ENA
resetr => rbuf[0]~reg0.ENA
resetr => rbuf[3]~reg0.ENA
resetr => rbuf[4]~reg0.ENA
resetr => rbuf[5]~reg0.ENA
resetr => rbuf[6]~reg0.ENA
resetr => rbuf[7]~reg0.ENA
resetr => r_ready~reg0.ENA
resetr => \pro2:rbufs[0].ENA
resetr => \pro2:rbufs[1].ENA
resetr => \pro2:rbufs[2].ENA
resetr => \pro2:rbufs[3].ENA
resetr => \pro2:rbufs[4].ENA
resetr => \pro2:rbufs[5].ENA
resetr => \pro2:rbufs[6].ENA
resetr => \pro2:rbufs[7].ENA
resetr => \pro2:rcnt[0].ENA
resetr => \pro2:rcnt[1].ENA
resetr => \pro2:rcnt[2].ENA
resetr => \pro2:rcnt[3].ENA
resetr => \pro2:rcnt[4].ENA
resetr => \pro2:rcnt[5].ENA
resetr => \pro2:rcnt[6].ENA
resetr => \pro2:rcnt[7].ENA
resetr => \pro2:rcnt[8].ENA
resetr => \pro2:rcnt[9].ENA
resetr => \pro2:rcnt[10].ENA
resetr => \pro2:rcnt[11].ENA
resetr => \pro2:rcnt[12].ENA
resetr => \pro2:rcnt[13].ENA
resetr => \pro2:rcnt[14].ENA
resetr => \pro2:rcnt[15].ENA
resetr => \pro2:rcnt[16].ENA
resetr => \pro2:rcnt[17].ENA
resetr => \pro2:rcnt[18].ENA
resetr => \pro2:rcnt[19].ENA
resetr => \pro2:rcnt[20].ENA
resetr => \pro2:rcnt[21].ENA
resetr => \pro2:rcnt[22].ENA
resetr => \pro2:rcnt[23].ENA
resetr => \pro2:rcnt[24].ENA
resetr => \pro2:rcnt[25].ENA
resetr => \pro2:rcnt[26].ENA
resetr => \pro2:rcnt[27].ENA
resetr => \pro2:rcnt[28].ENA
resetr => \pro2:rcnt[29].ENA
resetr => \pro2:rcnt[30].ENA
resetr => \pro2:rcnt[31].ENA
resetr => state~9.IN1
rxdr => rbufs~0.DATAB
rxdr => rbufs~1.DATAB
rxdr => rbufs~2.DATAB
rxdr => rbufs~3.DATAB
rxdr => rbufs~4.DATAB
rxdr => rbufs~5.DATAB
rxdr => rbufs~6.DATAB
rxdr => rbufs~7.DATAB
rxdr => Selector0.IN6
rxdr => Selector0.IN7
rxdr => state~0.OUTPUTSELECT
rxdr => Selector1.IN1
rxdr => rcnt~0.OUTPUTSELECT
rxdr => rcnt~1.OUTPUTSELECT
rxdr => rcnt~2.OUTPUTSELECT
rxdr => rcnt~3.OUTPUTSELECT
rxdr => rcnt~4.OUTPUTSELECT
rxdr => rcnt~5.OUTPUTSELECT
rxdr => rcnt~6.OUTPUTSELECT
rxdr => rcnt~7.OUTPUTSELECT
rxdr => rcnt~8.OUTPUTSELECT
rxdr => rcnt~9.OUTPUTSELECT
rxdr => rcnt~10.OUTPUTSELECT
rxdr => rcnt~11.OUTPUTSELECT
rxdr => rcnt~12.OUTPUTSELECT
rxdr => rcnt~13.OUTPUTSELECT
rxdr => rcnt~14.OUTPUTSELECT
rxdr => rcnt~15.OUTPUTSELECT
rxdr => rcnt~16.OUTPUTSELECT
rxdr => rcnt~17.OUTPUTSELECT
rxdr => rcnt~18.OUTPUTSELECT
rxdr => rcnt~19.OUTPUTSELECT
rxdr => rcnt~20.OUTPUTSELECT
rxdr => rcnt~21.OUTPUTSELECT
rxdr => rcnt~22.OUTPUTSELECT
rxdr => rcnt~23.OUTPUTSELECT
rxdr => rcnt~24.OUTPUTSELECT
rxdr => rcnt~25.OUTPUTSELECT
rxdr => rcnt~26.OUTPUTSELECT
rxdr => rcnt~27.OUTPUTSELECT
rxdr => rcnt~28.OUTPUTSELECT
rxdr => rcnt~29.OUTPUTSELECT
rxdr => rcnt~30.OUTPUTSELECT
rxdr => rcnt~31.OUTPUTSELECT
rxdr => count~7.OUTPUTSELECT
rxdr => count~6.OUTPUTSELECT
rxdr => count~5.OUTPUTSELECT
rxdr => count~4.OUTPUTSELECT
rxdr => state~1.OUTPUTSELECT
r_ready <= r_ready~reg0.DB_MAX_OUTPUT_PORT_TYPE
rbuf[0] <= rbuf[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
rbuf[1] <= rbuf[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
rbuf[2] <= rbuf[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
rbuf[3] <= rbuf[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
rbuf[4] <= rbuf[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
rbuf[5] <= rbuf[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
rbuf[6] <= rbuf[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
rbuf[7] <= rbuf[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE