uart.tan.qmsg

基于FPGA的UART实现 用VHDL编程

{ "Info" "ITDB_TSU_RESULT" "rxd:inst\|\\pro2:rbufs\[6\] reset clk 5.115 ns register " "Info: tsu for register \"rxd:inst\|\\pro2:rbufs\[6\]\" (data pin = \"reset\", clock pin = \"clk\") is 5.115 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "12.252 ns + Longest pin register " "Info: + Longest pin to register delay is 12.252 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns reset 1 PIN PIN_36 21 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_36; Fanout = 21; PIN Node = 'reset'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { reset } "NODE_NAME" } } { "UART.bdf" "" { Schematic "E:/毕设资料/程序/仿真/UART/UART.bdf" { { 8 -56 112 24 "reset" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.994 ns) + CELL(0.590 ns) 9.053 ns rxd:inst\|Decoder0~104 2 COMB LC_X17_Y9_N2 8 " "Info: 2: + IC(6.994 ns) + CELL(0.590 ns) = 9.053 ns; Loc. = LC_X17_Y9_N2; Fanout = 8; COMB Node = 'rxd:inst\|Decoder0~104'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "7.584 ns" { reset rxd:inst|Decoder0~104 } "NODE_NAME" } } { "rxd.vhd" "" { Text "E:/毕设资料/程序/仿真/UART/rxd.vhd" 52 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.389 ns) + CELL(0.292 ns) 10.734 ns rxd:inst\|Decoder0~106 3 COMB LC_X17_Y8_N8 1 " "Info: 3: + IC(1.389 ns) + CELL(0.292 ns) = 10.734 ns; Loc. = LC_X17_Y8_N8; Fanout = 1; COMB Node = 'rxd:inst\|Decoder0~106'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.681 ns" { rxd:inst|Decoder0~104 rxd:inst|Decoder0~106 } "NODE_NAME" } } { "rxd.vhd" "" { Text "E:/毕设资料/程序/仿真/UART/rxd.vhd" 52 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.209 ns) + CELL(0.309 ns) 12.252 ns rxd:inst\|\\pro2:rbufs\[6\] 4 REG LC_X18_Y9_N9 2 " "Info: 4: + IC(1.209 ns) + CELL(0.309 ns) = 12.252 ns; Loc. = LC_X18_Y9_N9; Fanout = 2; REG Node = 'rxd:inst\|\\pro2:rbufs\[6\]'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.518 ns" { rxd:inst|Decoder0~106 rxd:inst|\pro2:rbufs[6] } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.660 ns ( 21.71 % ) " "Info: Total cell delay = 2.660 ns ( 21.71 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.592 ns ( 78.29 % ) " "Info: Total interconnect delay = 9.592 ns ( 78.29 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "12.252 ns" { reset rxd:inst|Decoder0~104 rxd:inst|Decoder0~106 rxd:inst|\pro2:rbufs[6] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "12.252 ns" { reset reset~out0 rxd:inst|Decoder0~104 rxd:inst|Decoder0~106 rxd:inst|\pro2:rbufs[6] } { 0.000ns 0.000ns 6.994ns 1.389ns 1.209ns } { 0.000ns 1.469ns 0.590ns 0.292ns 0.309ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } {  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 7.174 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 7.174 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_17 33 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 33; CLK Node = 'clk'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "UART.bdf" "" { Schematic "E:/毕设资料/程序/仿真/UART/UART.bdf" { { 136 -152 16 152 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.560 ns) + CELL(0.935 ns) 2.964 ns fre:inst4\|bclk 2 REG LC_X8_Y6_N9 102 " "Info: 2: + IC(0.560 ns) + CELL(0.935 ns) = 2.964 ns; Loc. = LC_X8_Y6_N9; Fanout = 102; REG Node = 'fre:inst4\|bclk'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.495 ns" { clk fre:inst4|bclk } "NODE_NAME" } } { "fre.vhd" "" { Text "E:/毕设资料/程序/仿真/UART/fre.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.499 ns) + CELL(0.711 ns) 7.174 ns rxd:inst\|\\pro2:rbufs\[6\] 3 REG LC_X18_Y9_N9 2 " "Info: 3: + IC(3.499 ns) + CELL(0.711 ns) = 7.174 ns; Loc. = LC_X18_Y9_N9; Fanout = 2; REG Node = 'rxd:inst\|\\pro2:rbufs\[6\]'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "4.210 ns" { fre:inst4|bclk rxd:inst|\pro2:rbufs[6] } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 43.42 % ) " "Info: Total cell delay = 3.115 ns ( 43.42 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.059 ns ( 56.58 % ) " "Info: Total interconnect delay = 4.059 ns ( 56.58 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "7.174 ns" { clk fre:inst4|bclk rxd:inst|\pro2:rbufs[6] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "7.174 ns" { clk clk~out0 fre:inst4|bclk rxd:inst|\pro2:rbufs[6] } { 0.000ns 0.000ns 0.560ns 3.499ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "12.252 ns" { reset rxd:inst|Decoder0~104 rxd:inst|Decoder0~106 rxd:inst|\pro2:rbufs[6] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "12.252 ns" { reset reset~out0 rxd:inst|Decoder0~104 rxd:inst|Decoder0~106 rxd:inst|\pro2:rbufs[6] } { 0.000ns 0.000ns 6.994ns 1.389ns 1.209ns } { 0.000ns 1.469ns 0.590ns 0.292ns 0.309ns } "" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "7.174 ns" { clk fre:inst4|bclk rxd:inst|\pro2:rbufs[6] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "7.174 ns" { clk clk~out0 fre:inst4|bclk rxd:inst|\pro2:rbufs[6] } { 0.000ns 0.000ns 0.560ns 3.499ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk txd txd:inst1\|txds 11.688 ns register " "Info: tco from clock \"clk\" to destination pin \"txd\" through register \"txd:inst1\|txds\" is 11.688 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 7.174 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 7.174 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_17 33 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 33; CLK Node = 'clk'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "UART.bdf" "" { Schematic "E:/毕设资料/程序/仿真/UART/UART.bdf" { { 136 -152 16 152 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.560 ns) + CELL(0.935 ns) 2.964 ns fre:inst4\|bclk 2 REG LC_X8_Y6_N9 102 " "Info: 2: + IC(0.560 ns) + CELL(0.935 ns) = 2.964 ns; Loc. = LC_X8_Y6_N9; Fanout = 102; REG Node = 'fre:inst4\|bclk'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.495 ns" { clk fre:inst4|bclk } "NODE_NAME" } } { "fre.vhd" "" { Text "E:/毕设资料/程序/仿真/UART/fre.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.499 ns) + CELL(0.711 ns) 7.174 ns txd:inst1\|txds 3 REG LC_X21_Y11_N5 2 " "Info: 3: + IC(3.499 ns) + CELL(0.711 ns) = 7.174 ns; Loc. = LC_X21_Y11_N5; Fanout = 2; REG Node = 'txd:inst1\|txds'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "4.210 ns" { fre:inst4|bclk txd:inst1|txds } "NODE_NAME" } } { "txd.vhd" "" { Text "E:/毕设资料/程序/仿真/UART/txd.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 43.42 % ) " "Info: Total cell delay = 3.115 ns ( 43.42 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.059 ns ( 56.58 % ) " "Info: Total interconnect delay = 4.059 ns ( 56.58 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "7.174 ns" { clk fre:inst4|bclk txd:inst1|txds } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "7.174 ns" { clk clk~out0 fre:inst4|bclk txd:inst1|txds } { 0.000ns 0.000ns 0.560ns 3.499ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "txd.vhd" "" { Text "E:/毕设资料/程序/仿真/UART/txd.vhd" 22 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.290 ns + Longest register pin " "Info: + Longest register to pin delay is 4.290 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns txd:inst1\|txds 1 REG LC_X21_Y11_N5 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X21_Y11_N5; Fanout = 2; REG Node = 'txd:inst1\|txds'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { txd:inst1|txds } "NODE_NAME" } } { "txd.vhd" "" { Text "E:/毕设资料/程序/仿真/UART/txd.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.166 ns) + CELL(2.124 ns) 4.290 ns txd 2 PIN PIN_85 0 " "Info: 2: + IC(2.166 ns) + CELL(2.124 ns) = 4.290 ns; Loc. = PIN_85; Fanout = 0; PIN Node = 'txd'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "4.290 ns" { txd:inst1|txds txd } "NODE_NAME" } } { "UART.bdf" "" { Schematic "E:/毕设资料/程序/仿真/UART/UART.bdf" { { -24 472 648 -8 "txd" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.124 ns ( 49.51 % ) " "Info: Total cell delay = 2.124 ns ( 49.51 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.166 ns ( 50.49 % ) " "Info: Total interconnect delay = 2.166 ns ( 50.49 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "4.290 ns" { txd:inst1|txds txd } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "4.290 ns" { txd:inst1|txds txd } { 0.000ns 2.166ns } { 0.000ns 2.124ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "7.174 ns" { clk fre:inst4|bclk txd:inst1|txds } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "7.174 ns" { clk clk~out0 fre:inst4|bclk txd:inst1|txds } { 0.000ns 0.000ns 0.560ns 3.499ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "4.290 ns" { txd:inst1|txds txd } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "4.290 ns" { txd:inst1|txds txd } { 0.000ns 2.166ns } { 0.000ns 2.124ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "rxd:inst\|\\pro2:rbufs\[4\] rxd clk -0.973 ns register " "Info: th for register \"rxd:inst\|\\pro2:rbufs\[4\]\" (data pin = \"rxd\", clock pin = \"clk\") is -0.973 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 7.174 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 7.174 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_17 33 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 33; CLK Node = 'clk'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "UART.bdf" "" { Schematic "E:/毕设资料/程序/仿真/UART/UART.bdf" { { 136 -152 16 152 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.560 ns) + CELL(0.935 ns) 2.964 ns fre:inst4\|bclk 2 REG LC_X8_Y6_N9 102 " "Info: 2: + IC(0.560 ns) + CELL(0.935 ns) = 2.964 ns; Loc. = LC_X8_Y6_N9; Fanout = 102; REG Node = 'fre:inst4\|bclk'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.495 ns" { clk fre:inst4|bclk } "NODE_NAME" } } { "fre.vhd" "" { Text "E:/毕设资料/程序/仿真/UART/fre.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.499 ns) + CELL(0.711 ns) 7.174 ns rxd:inst\|\\pro2:rbufs\[4\] 3 REG LC_X17_Y8_N7 2 " "Info: 3: + IC(3.499 ns) + CELL(0.711 ns) = 7.174 ns; Loc. = LC_X17_Y8_N7; Fanout = 2; REG Node = 'rxd:inst\|\\pro2:rbufs\[4\]'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "4.210 ns" { fre:inst4|bclk rxd:inst|\pro2:rbufs[4] } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 43.42 % ) " "Info: Total cell delay = 3.115 ns ( 43.42 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.059 ns ( 56.58 % ) " "Info: Total interconnect delay = 4.059 ns ( 56.58 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "7.174 ns" { clk fre:inst4|bclk rxd:inst|\pro2:rbufs[4] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "7.174 ns" { clk clk~out0 fre:inst4|bclk rxd:inst|\pro2:rbufs[4] } { 0.000ns 0.000ns 0.560ns 3.499ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } {  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.162 ns - Shortest pin register " "Info: - Shortest pin to register delay is 8.162 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns rxd 1 PIN PIN_91 13 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_91; Fanout = 13; PIN Node = 'rxd'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { rxd } "NODE_NAME" } } { "UART.bdf" "" { Schematic "E:/毕设资料/程序/仿真/UART/UART.bdf" { { 24 -56 112 40 "rxd" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.215 ns) + CELL(0.478 ns) 8.162 ns rxd:inst\|\\pro2:rbufs\[4\] 2 REG LC_X17_Y8_N7 2 " "Info: 2: + IC(6.215 ns) + CELL(0.478 ns) = 8.162 ns; Loc. = LC_X17_Y8_N7; Fanout = 2; REG Node = 'rxd:inst\|\\pro2:rbufs\[4\]'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "6.693 ns" { rxd rxd:inst|\pro2:rbufs[4] } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.947 ns ( 23.85 % ) " "Info: Total cell delay = 1.947 ns ( 23.85 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.215 ns ( 76.15 % ) " "Info: Total interconnect delay = 6.215 ns ( 76.15 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "8.162 ns" { rxd rxd:inst|\pro2:rbufs[4] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "8.162 ns" { rxd rxd~out0 rxd:inst|\pro2:rbufs[4] } { 0.000ns 0.000ns 6.215ns } { 0.000ns 1.469ns 0.478ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "7.174 ns" { clk fre:inst4|bclk rxd:inst|\pro2:rbufs[4] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "7.174 ns" { clk clk~out0 fre:inst4|bclk rxd:inst|\pro2:rbufs[4] } { 0.000ns 0.000ns 0.560ns 3.499ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "8.162 ns" { rxd rxd:inst|\pro2:rbufs[4] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "8.162 ns" { rxd rxd~out0 rxd:inst|\pro2:rbufs[4] } { 0.000ns 0.000ns 6.215ns } { 0.000ns 1.469ns 0.478ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}