📄 uart.tan.qmsg

📁 基于FPGA的UART实现用VHDL编程
💻 QMSG
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{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "fre:inst4\|bclk " "Info: Detected ripple clock \"fre:inst4\|bclk\" as buffer" {  } { { "fre.vhd" "" { Text "E:/毕设资料/程序/仿真/UART/fre.vhd" 8 -1 0 } } { "d:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "fre:inst4\|bclk" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITDB_FULL_SLACK_RESULT" "clk register fre:inst4\|count\[12\] register fre:inst4\|bclk 34.643 ns " "Info: Slack time is 34.643 ns for clock \"clk\" between source register \"fre:inst4\|count\[12\]\" and destination register \"fre:inst4\|bclk\"" { { "Info" "ITDB_SIMPLE_FMAX_RESULT" "142.39 MHz 7.023 ns " "Info: Fmax is 142.39 MHz (period= 7.023 ns)" {  } {  } 0 0 "Fmax is %1!s! (period= %2!s!)" 0 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "41.405 ns + Largest register register " "Info: + Largest register to register requirement is 41.405 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "41.666 ns + " "Info: + Setup relationship between source and destination is 41.666 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 41.666 ns " "Info: + Latch edge is 41.666 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination clk 41.666 ns 0.000 ns  50 " "Info: Clock period of Destination clock \"clk\" is 41.666 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0} { "Info" "ITDB_EDGE_RESULT" "- Launch 0.000 ns " "Info: - Launch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source clk 41.666 ns 0.000 ns  50 " "Info: Clock period of Source clock \"clk\" is 41.666 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0}  } {  } 0 0 "%2!c! Setup relationship between source and destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns + Largest " "Info: + Largest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.740 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.740 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_17 33 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 33; CLK Node = 'clk'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "UART.bdf" "" { Schematic "E:/毕设资料/程序/仿真/UART/UART.bdf" { { 136 -152 16 152 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.560 ns) + CELL(0.711 ns) 2.740 ns fre:inst4\|bclk 2 REG LC_X8_Y6_N9 102 " "Info: 2: + IC(0.560 ns) + CELL(0.711 ns) = 2.740 ns; Loc. = LC_X8_Y6_N9; Fanout = 102; REG Node = 'fre:inst4\|bclk'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.271 ns" { clk fre:inst4|bclk } "NODE_NAME" } } { "fre.vhd" "" { Text "E:/毕设资料/程序/仿真/UART/fre.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 79.56 % ) " "Info: Total cell delay = 2.180 ns ( 79.56 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.560 ns ( 20.44 % ) " "Info: Total interconnect delay = 0.560 ns ( 20.44 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.740 ns" { clk fre:inst4|bclk } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.740 ns" { clk clk~out0 fre:inst4|bclk } { 0.000ns 0.000ns 0.560ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.740 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.740 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_17 33 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 33; CLK Node = 'clk'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "UART.bdf" "" { Schematic "E:/毕设资料/程序/仿真/UART/UART.bdf" { { 136 -152 16 152 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.560 ns) + CELL(0.711 ns) 2.740 ns fre:inst4\|count\[12\] 2 REG LC_X9_Y8_N2 4 " "Info: 2: + IC(0.560 ns) + CELL(0.711 ns) = 2.740 ns; Loc. = LC_X9_Y8_N2; Fanout = 4; REG Node = 'fre:inst4\|count\[12\]'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.271 ns" { clk fre:inst4|count[12] } "NODE_NAME" } } { "fre.vhd" "" { Text "E:/毕设资料/程序/仿真/UART/fre.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 79.56 % ) " "Info: Total cell delay = 2.180 ns ( 79.56 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.560 ns ( 20.44 % ) " "Info: Total interconnect delay = 0.560 ns ( 20.44 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.740 ns" { clk fre:inst4|count[12] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.740 ns" { clk clk~out0 fre:inst4|count[12] } { 0.000ns 0.000ns 0.560ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.740 ns" { clk fre:inst4|bclk } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.740 ns" { clk clk~out0 fre:inst4|bclk } { 0.000ns 0.000ns 0.560ns } { 0.000ns 1.469ns 0.711ns } "" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.740 ns" { clk fre:inst4|count[12] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.740 ns" { clk clk~out0 fre:inst4|count[12] } { 0.000ns 0.000ns 0.560ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns - " "Info: - Micro clock to output delay of source is 0.224 ns" {  } { { "fre.vhd" "" { Text "E:/毕设资料/程序/仿真/UART/fre.vhd" 15 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns - " "Info: - Micro setup delay of destination is 0.037 ns" {  } { { "fre.vhd" "" { Text "E:/毕设资料/程序/仿真/UART/fre.vhd" 8 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.740 ns" { clk fre:inst4|bclk } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.740 ns" { clk clk~out0 fre:inst4|bclk } { 0.000ns 0.000ns 0.560ns } { 0.000ns 1.469ns 0.711ns } "" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.740 ns" { clk fre:inst4|count[12] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.740 ns" { clk clk~out0 fre:inst4|count[12] } { 0.000ns 0.000ns 0.560ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.762 ns - Longest register register " "Info: - Longest register to register delay is 6.762 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns fre:inst4\|count\[12\] 1 REG LC_X9_Y8_N2 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X9_Y8_N2; Fanout = 4; REG Node = 'fre:inst4\|count\[12\]'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { fre:inst4|count[12] } "NODE_NAME" } } { "fre.vhd" "" { Text "E:/毕设资料/程序/仿真/UART/fre.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.530 ns) + CELL(0.590 ns) 1.120 ns fre:inst4\|Equal0~304 2 COMB LC_X9_Y8_N7 1 " "Info: 2: + IC(0.530 ns) + CELL(0.590 ns) = 1.120 ns; Loc. = LC_X9_Y8_N7; Fanout = 1; COMB Node = 'fre:inst4\|Equal0~304'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.120 ns" { fre:inst4|count[12] fre:inst4|Equal0~304 } "NODE_NAME" } } { "fre.vhd" "" { Text "E:/毕设资料/程序/仿真/UART/fre.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.432 ns) + CELL(0.590 ns) 2.142 ns fre:inst4\|Equal0~305 3 COMB LC_X9_Y8_N0 1 " "Info: 3: + IC(0.432 ns) + CELL(0.590 ns) = 2.142 ns; Loc. = LC_X9_Y8_N0; Fanout = 1; COMB Node = 'fre:inst4\|Equal0~305'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.022 ns" { fre:inst4|Equal0~304 fre:inst4|Equal0~305 } "NODE_NAME" } } { "fre.vhd" "" { Text "E:/毕设资料/程序/仿真/UART/fre.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.534 ns) + CELL(0.590 ns) 4.266 ns fre:inst4\|Equal0~306 4 COMB LC_X10_Y9_N0 2 " "Info: 4: + IC(1.534 ns) + CELL(0.590 ns) = 4.266 ns; Loc. = LC_X10_Y9_N0; Fanout = 2; COMB Node = 'fre:inst4\|Equal0~306'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.124 ns" { fre:inst4|Equal0~305 fre:inst4|Equal0~306 } "NODE_NAME" } } { "fre.vhd" "" { Text "E:/毕设资料/程序/仿真/UART/fre.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.182 ns) + CELL(0.114 ns) 4.562 ns fre:inst4\|Equal0~309 5 COMB LC_X10_Y9_N1 5 " "Info: 5: + IC(0.182 ns) + CELL(0.114 ns) = 4.562 ns; Loc. = LC_X10_Y9_N1; Fanout = 5; COMB Node = 'fre:inst4\|Equal0~309'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.296 ns" { fre:inst4|Equal0~306 fre:inst4|Equal0~309 } "NODE_NAME" } } { "fre.vhd" "" { Text "E:/毕设资料/程序/仿真/UART/fre.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.593 ns) + CELL(0.607 ns) 6.762 ns fre:inst4\|bclk 6 REG LC_X8_Y6_N9 102 " "Info: 6: + IC(1.593 ns) + CELL(0.607 ns) = 6.762 ns; Loc. = LC_X8_Y6_N9; Fanout = 102; REG Node = 'fre:inst4\|bclk'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.200 ns" { fre:inst4|Equal0~309 fre:inst4|bclk } "NODE_NAME" } } { "fre.vhd" "" { Text "E:/毕设资料/程序/仿真/UART/fre.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.491 ns ( 36.84 % ) " "Info: Total cell delay = 2.491 ns ( 36.84 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.271 ns ( 63.16 % ) " "Info: Total interconnect delay = 4.271 ns ( 63.16 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "6.762 ns" { fre:inst4|count[12] fre:inst4|Equal0~304 fre:inst4|Equal0~305 fre:inst4|Equal0~306 fre:inst4|Equal0~309 fre:inst4|bclk } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "6.762 ns" { fre:inst4|count[12] fre:inst4|Equal0~304 fre:inst4|Equal0~305 fre:inst4|Equal0~306 fre:inst4|Equal0~309 fre:inst4|bclk } { 0.000ns 0.530ns 0.432ns 1.534ns 0.182ns 1.593ns } { 0.000ns 0.590ns 0.590ns 0.590ns 0.114ns 0.607ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.740 ns" { clk fre:inst4|bclk } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.740 ns" { clk clk~out0 fre:inst4|bclk } { 0.000ns 0.000ns 0.560ns } { 0.000ns 1.469ns 0.711ns } "" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.740 ns" { clk fre:inst4|count[12] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.740 ns" { clk clk~out0 fre:inst4|count[12] } { 0.000ns 0.000ns 0.560ns } { 0.000ns 1.469ns 0.711ns } "" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "6.762 ns" { fre:inst4|count[12] fre:inst4|Equal0~304 fre:inst4|Equal0~305 fre:inst4|Equal0~306 fre:inst4|Equal0~309 fre:inst4|bclk } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "6.762 ns" { fre:inst4|count[12] fre:inst4|Equal0~304 fre:inst4|Equal0~305 fre:inst4|Equal0~306 fre:inst4|Equal0~309 fre:inst4|bclk } { 0.000ns 0.530ns 0.432ns 1.534ns 0.182ns 1.593ns } { 0.000ns 0.590ns 0.590ns 0.590ns 0.114ns 0.607ns } "" } }  } 0 0 "Slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0}
{ "Info" "ITDB_FULL_MIN_SLACK_RESULT" "clk register rxd:inst\|\\pro2:rbufs\[6\] register rxd:inst\|rbuf\[6\] 874 ps " "Info: Minimum slack time is 874 ps for clock \"clk\" between source register \"rxd:inst\|\\pro2:rbufs\[6\]\" and destination register \"rxd:inst\|rbuf\[6\]\"" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.665 ns + Shortest register register " "Info: + Shortest register to register delay is 0.665 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns rxd:inst\|\\pro2:rbufs\[6\] 1 REG LC_X18_Y9_N9 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X18_Y9_N9; Fanout = 2; REG Node = 'rxd:inst\|\\pro2:rbufs\[6\]'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { rxd:inst|\pro2:rbufs[6] } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.550 ns) + CELL(0.115 ns) 0.665 ns rxd:inst\|rbuf\[6\] 2 REG LC_X18_Y9_N7 1 " "Info: 2: + IC(0.550 ns) + CELL(0.115 ns) = 0.665 ns; Loc. = LC_X18_Y9_N7; Fanout = 1; REG Node = 'rxd:inst\|rbuf\[6\]'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.665 ns" { rxd:inst|\pro2:rbufs[6] rxd:inst|rbuf[6] } "NODE_NAME" } } { "rxd.vhd" "" { Text "E:/毕设资料/程序/仿真/UART/rxd.vhd" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.115 ns ( 17.29 % ) " "Info: Total cell delay = 0.115 ns ( 17.29 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.550 ns ( 82.71 % ) " "Info: Total interconnect delay = 0.550 ns ( 82.71 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.665 ns" { rxd:inst|\pro2:rbufs[6] rxd:inst|rbuf[6] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "0.665 ns" { rxd:inst|\pro2:rbufs[6] rxd:inst|rbuf[6] } { 0.000ns 0.550ns } { 0.000ns 0.115ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "-0.209 ns - Smallest register register " "Info: - Smallest register to register requirement is -0.209 ns" { { "Info" "ITDB_FULL_HOLD_REQUIREMENT" "0.000 ns + " "Info: + Hold relationship between source and destination is 0.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 0.000 ns " "Info: + Latch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination clk 41.666 ns 0.000 ns  50 " "Info: Clock period of Destination clock \"clk\" is 41.666 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Hold 1 " "Info: Multicycle Hold factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0} { "Info" "ITDB_EDGE_RESULT" "- Launch 0.000 ns " "Info: - Launch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source clk 41.666 ns 0.000 ns  50 " "Info: Clock period of Source clock \"clk\" is 41.666 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Hold 1 " "Info: Multicycle Hold factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0}  } {  } 0 0 "%2!c! Hold relationship between source and destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns + Smallest " "Info: + Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 7.174 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 7.174 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_17 33 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 33; CLK Node = 'clk'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "UART.bdf" "" { Schematic "E:/毕设资料/程序/仿真/UART/UART.bdf" { { 136 -152 16 152 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.560 ns) + CELL(0.935 ns) 2.964 ns fre:inst4\|bclk 2 REG LC_X8_Y6_N9 102 " "Info: 2: + IC(0.560 ns) + CELL(0.935 ns) = 2.964 ns; Loc. = LC_X8_Y6_N9; Fanout = 102; REG Node = 'fre:inst4\|bclk'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.495 ns" { clk fre:inst4|bclk } "NODE_NAME" } } { "fre.vhd" "" { Text "E:/毕设资料/程序/仿真/UART/fre.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.499 ns) + CELL(0.711 ns) 7.174 ns rxd:inst\|rbuf\[6\] 3 REG LC_X18_Y9_N7 1 " "Info: 3: + IC(3.499 ns) + CELL(0.711 ns) = 7.174 ns; Loc. = LC_X18_Y9_N7; Fanout = 1; REG Node = 'rxd:inst\|rbuf\[6\]'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "4.210 ns" { fre:inst4|bclk rxd:inst|rbuf[6] } "NODE_NAME" } } { "rxd.vhd" "" { Text "E:/毕设资料/程序/仿真/UART/rxd.vhd" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 43.42 % ) " "Info: Total cell delay = 3.115 ns ( 43.42 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.059 ns ( 56.58 % ) " "Info: Total interconnect delay = 4.059 ns ( 56.58 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "7.174 ns" { clk fre:inst4|bclk rxd:inst|rbuf[6] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "7.174 ns" { clk clk~out0 fre:inst4|bclk rxd:inst|rbuf[6] } { 0.000ns 0.000ns 0.560ns 3.499ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 7.174 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to source register is 7.174 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_17 33 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 33; CLK Node = 'clk'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "UART.bdf" "" { Schematic "E:/毕设资料/程序/仿真/UART/UART.bdf" { { 136 -152 16 152 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.560 ns) + CELL(0.935 ns) 2.964 ns fre:inst4\|bclk 2 REG LC_X8_Y6_N9 102 " "Info: 2: + IC(0.560 ns) + CELL(0.935 ns) = 2.964 ns; Loc. = LC_X8_Y6_N9; Fanout = 102; REG Node = 'fre:inst4\|bclk'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.495 ns" { clk fre:inst4|bclk } "NODE_NAME" } } { "fre.vhd" "" { Text "E:/毕设资料/程序/仿真/UART/fre.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.499 ns) + CELL(0.711 ns) 7.174 ns rxd:inst\|\\pro2:rbufs\[6\] 3 REG LC_X18_Y9_N9 2 " "Info: 3: + IC(3.499 ns) + CELL(0.711 ns) = 7.174 ns; Loc. = LC_X18_Y9_N9; Fanout = 2; REG Node = 'rxd:inst\|\\pro2:rbufs\[6\]'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "4.210 ns" { fre:inst4|bclk rxd:inst|\pro2:rbufs[6] } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 43.42 % ) " "Info: Total cell delay = 3.115 ns ( 43.42 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.059 ns ( 56.58 % ) " "Info: Total interconnect delay = 4.059 ns ( 56.58 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "7.174 ns" { clk fre:inst4|bclk rxd:inst|\pro2:rbufs[6] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "7.174 ns" { clk clk~out0 fre:inst4|bclk rxd:inst|\pro2:rbufs[6] } { 0.000ns 0.000ns 0.560ns 3.499ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "7.174 ns" { clk fre:inst4|bclk rxd:inst|rbuf[6] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "7.174 ns" { clk clk~out0 fre:inst4|bclk rxd:inst|rbuf[6] } { 0.000ns 0.000ns 0.560ns 3.499ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "7.174 ns" { clk fre:inst4|bclk rxd:inst|\pro2:rbufs[6] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "7.174 ns" { clk clk~out0 fre:inst4|bclk rxd:inst|\pro2:rbufs[6] } { 0.000ns 0.000ns 0.560ns 3.499ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns - " "Info: - Micro clock to output delay of source is 0.224 ns" {  } {  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "rxd.vhd" "" { Text "E:/毕设资料/程序/仿真/UART/rxd.vhd" 30 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "7.174 ns" { clk fre:inst4|bclk rxd:inst|rbuf[6] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "7.174 ns" { clk clk~out0 fre:inst4|bclk rxd:inst|rbuf[6] } { 0.000ns 0.000ns 0.560ns 3.499ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "7.174 ns" { clk fre:inst4|bclk rxd:inst|\pro2:rbufs[6] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "7.174 ns" { clk clk~out0 fre:inst4|bclk rxd:inst|\pro2:rbufs[6] } { 0.000ns 0.000ns 0.560ns 3.499ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.665 ns" { rxd:inst|\pro2:rbufs[6] rxd:inst|rbuf[6] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "0.665 ns" { rxd:inst|\pro2:rbufs[6] rxd:inst|rbuf[6] } { 0.000ns 0.550ns } { 0.000ns 0.115ns } "" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "7.174 ns" { clk fre:inst4|bclk rxd:inst|rbuf[6] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "7.174 ns" { clk clk~out0 fre:inst4|bclk rxd:inst|rbuf[6] } { 0.000ns 0.000ns 0.560ns 3.499ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "7.174 ns" { clk fre:inst4|bclk rxd:inst|\pro2:rbufs[6] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "7.174 ns" { clk clk~out0 fre:inst4|bclk rxd:inst|\pro2:rbufs[6] } { 0.000ns 0.000ns 0.560ns 3.499ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } }  } 0 0 "Minimum slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0}
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