uart.fnsim.qmsg

基于FPGA的UART实现 用VHDL编程

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Functional Simulation Netlist Generation Quartus II " "Info: Running Quartus II Functional Simulation Netlist Generation" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.0 Build 33 02/05/2007 SJ Full Version " "Info: Version 7.0 Build 33 02/05/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Aug 07 23:21:55 2007 " "Info: Processing started: Tue Aug 07 23:21:55 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off UART -c UART --generate_functional_sim_netlist " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off UART -c UART --generate_functional_sim_netlist" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "rxd.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file rxd.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 rxd-Behavioral " "Info: Found design unit 1: rxd-Behavioral" {  } { { "rxd.vhd" "" { Text "E:/毕设资料/程序/仿真/UART/rxd.vhd" 13 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 rxd " "Info: Found entity 1: rxd" {  } { { "rxd.vhd" "" { Text "E:/毕设资料/程序/仿真/UART/rxd.vhd" 6 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "txd.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file txd.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 txd-Behavioral " "Info: Found design unit 1: txd-Behavioral" {  } { { "txd.vhd" "" { Text "E:/毕设资料/程序/仿真/UART/txd.vhd" 13 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 txd " "Info: Found entity 1: txd" {  } { { "txd.vhd" "" { Text "E:/毕设资料/程序/仿真/UART/txd.vhd" 6 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "fre.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file fre.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 fre-Behavioral " "Info: Found design unit 1: fre-Behavioral" {  } { { "fre.vhd" "" { Text "E:/毕设资料/程序/仿真/UART/fre.vhd" 10 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 fre " "Info: Found entity 1: fre" {  } { { "fre.vhd" "" { Text "E:/毕设资料/程序/仿真/UART/fre.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "UART.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file UART.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 UART " "Info: Found entity 1: UART" {  } { { "UART.bdf" "" { Schematic "E:/毕设资料/程序/仿真/UART/UART.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "UART " "Info: Elaborating entity \"UART\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "txd txd:inst1 " "Info: Elaborating entity \"txd\" for hierarchy \"txd:inst1\"" {  } { { "UART.bdf" "inst1" { Schematic "E:/毕设资料/程序/仿真/UART/UART.bdf" { { -48 392 520 80 "inst1" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "fre fre:inst4 " "Info: Elaborating entity \"fre\" for hierarchy \"fre:inst4\"" {  } { { "UART.bdf" "inst4" { Schematic "E:/毕设资料/程序/仿真/UART/UART.bdf" { { 112 -40 56 208 "inst4" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "rxd rxd:inst " "Info: Elaborating entity \"rxd\" for hierarchy \"rxd:inst\"" {  } { { "UART.bdf" "inst" { Schematic "E:/毕设资料/程序/仿真/UART/UART.bdf" { { -32 152 280 64 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/70/quartus/libraries/megafunctions/lpm_add_sub.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/70/quartus/libraries/megafunctions/lpm_add_sub.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_add_sub " "Info: Found entity 1: lpm_add_sub" {  } { { "lpm_add_sub.tdf" "" { Text "d:/altera/70/quartus/libraries/megafunctions/lpm_add_sub.tdf" 102 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "rxd:inst\|lpm_add_sub:Add0 " "Info: Elaborated megafunction instantiation \"rxd:inst\|lpm_add_sub:Add0\"" {  } { { "d:/altera/70/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "d:/altera/70/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/70/quartus/libraries/megafunctions/addcore.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/70/quartus/libraries/megafunctions/addcore.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 addcore " "Info: Found entity 1: addcore" {  } { { "addcore.tdf" "" { Text "d:/altera/70/quartus/libraries/megafunctions/addcore.tdf" 73 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "rxd:inst\|lpm_add_sub:Add0\|addcore:adder rxd:inst\|lpm_add_sub:Add0 " "Info: Elaborated megafunction instantiation \"rxd:inst\|lpm_add_sub:Add0\|addcore:adder\", which is child of megafunction instantiation \"rxd:inst\|lpm_add_sub:Add0\"" {  } { { "lpm_add_sub.tdf" "" { Text "d:/altera/70/quartus/libraries/megafunctions/lpm_add_sub.tdf" 268 4 0 } } { "d:/altera/70/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "d:/altera/70/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "rxd:inst\|lpm_add_sub:Add0 " "Info: Instantiated megafunction \"rxd:inst\|lpm_add_sub:Add0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 4 " "Info: Parameter \"LPM_WIDTH\" = \"4\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION ADD " "Info: Parameter \"LPM_DIRECTION\" = \"ADD\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Info: Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ONE_INPUT_IS_CONSTANT YES " "Info: Parameter \"ONE_INPUT_IS_CONSTANT\" = \"YES\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0}  } { { "d:/altera/70/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "d:/altera/70/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/70/quartus/libraries/megafunctions/a_csnbuffer.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/70/quartus/libraries/megafunctions/a_csnbuffer.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_csnbuffer " "Info: Found entity 1: a_csnbuffer" {  } { { "a_csnbuffer.tdf" "" { Text "d:/altera/70/quartus/libraries/megafunctions/a_csnbuffer.tdf" 10 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}