uart.sim.qmsg

基于FPGA的UART实现 用VHDL编程

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Simulator Quartus II " "Info: Running Quartus II Simulator" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.0 Build 33 02/05/2007 SJ Full Version " "Info: Version 7.0 Build 33 02/05/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Aug 10 08:25:56 2007 " "Info: Processing started: Fri Aug 10 08:25:56 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sim --read_settings_files=on --write_settings_files=off UART -c UART " "Info: Command: quartus_sim --read_settings_files=on --write_settings_files=off UART -c UART" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISDB_SOURCE_VECTOR_FILE_USED" "E:/毕设资料/程序/仿真/UART/UART.vwf " "Info: Using vector source file \"E:/毕设资料/程序/仿真/UART/UART.vwf\"" {  } {  } 0 0 "Using vector source file \"%1!s!\"" 0 0}
{ "Info" "ISDB_OVERWRITE_WAVEFORM_INPUTS_WITH_SIMULATION_OUTPUTS" "" "Info: Overwriting simulation input file with simulation results" { { "Info" "ISDB_SOURCE_VECTOR_FILE_BACKUP" "UART.vwf UART.sim_ori.vwf " "Info: A backup of UART.vwf called UART.sim_ori.vwf has been created in the db folder" {  } {  } 0 0 "A backup of %1!s! called %2!s! has been created in the db folder" 0 0}  } {  } 0 0 "Overwriting simulation input file with simulation results" 0 0}
{ "Warning" "WSIM_NO_INAME_FOR_CHANNEL" "mid\[7\] " "Warning: Ignored node in vector source file. Can't find corresponding node name \"mid\[7\]\" in design." {  } { { "E:/毕设资料/程序/仿真/UART/UART.vwf" "" { Waveform "E:/毕设资料/程序/仿真/UART/UART.vwf" "mid\[7\]" "0 ps" "0 ps" "" } }  } 0 0 "Ignored node in vector source file. Can't find corresponding node name \"%1!s!\" in design." 0 0}
{ "Warning" "WSIM_NO_INAME_FOR_CHANNEL" "mid\[6\] " "Warning: Ignored node in vector source file. Can't find corresponding node name \"mid\[6\]\" in design." {  } { { "E:/毕设资料/程序/仿真/UART/UART.vwf" "" { Waveform "E:/毕设资料/程序/仿真/UART/UART.vwf" "mid\[6\]" "0 ps" "0 ps" "" } }  } 0 0 "Ignored node in vector source file. Can't find corresponding node name \"%1!s!\" in design." 0 0}
{ "Warning" "WSIM_NO_INAME_FOR_CHANNEL" "mid\[5\] " "Warning: Ignored node in vector source file. Can't find corresponding node name \"mid\[5\]\" in design." {  } { { "E:/毕设资料/程序/仿真/UART/UART.vwf" "" { Waveform "E:/毕设资料/程序/仿真/UART/UART.vwf" "mid\[5\]" "0 ps" "0 ps" "" } }  } 0 0 "Ignored node in vector source file. Can't find corresponding node name \"%1!s!\" in design." 0 0}
{ "Warning" "WSIM_NO_INAME_FOR_CHANNEL" "mid\[4\] " "Warning: Ignored node in vector source file. Can't find corresponding node name \"mid\[4\]\" in design." {  } { { "E:/毕设资料/程序/仿真/UART/UART.vwf" "" { Waveform "E:/毕设资料/程序/仿真/UART/UART.vwf" "mid\[4\]" "0 ps" "0 ps" "" } }  } 0 0 "Ignored node in vector source file. Can't find corresponding node name \"%1!s!\" in design." 0 0}
{ "Warning" "WSIM_NO_INAME_FOR_CHANNEL" "mid\[3\] " "Warning: Ignored node in vector source file. Can't find corresponding node name \"mid\[3\]\" in design." {  } { { "E:/毕设资料/程序/仿真/UART/UART.vwf" "" { Waveform "E:/毕设资料/程序/仿真/UART/UART.vwf" "mid\[3\]" "0 ps" "0 ps" "" } }  } 0 0 "Ignored node in vector source file. Can't find corresponding node name \"%1!s!\" in design." 0 0}
{ "Warning" "WSIM_NO_INAME_FOR_CHANNEL" "mid\[2\] " "Warning: Ignored node in vector source file. Can't find corresponding node name \"mid\[2\]\" in design." {  } { { "E:/毕设资料/程序/仿真/UART/UART.vwf" "" { Waveform "E:/毕设资料/程序/仿真/UART/UART.vwf" "mid\[2\]" "0 ps" "0 ps" "" } }  } 0 0 "Ignored node in vector source file. Can't find corresponding node name \"%1!s!\" in design." 0 0}
{ "Warning" "WSIM_NO_INAME_FOR_CHANNEL" "mid\[1\] " "Warning: Ignored node in vector source file. Can't find corresponding node name \"mid\[1\]\" in design." {  } { { "E:/毕设资料/程序/仿真/UART/UART.vwf" "" { Waveform "E:/毕设资料/程序/仿真/UART/UART.vwf" "mid\[1\]" "0 ps" "0 ps" "" } }  } 0 0 "Ignored node in vector source file. Can't find corresponding node name \"%1!s!\" in design." 0 0}
{ "Warning" "WSIM_NO_INAME_FOR_CHANNEL" "mid\[0\] " "Warning: Ignored node in vector source file. Can't find corresponding node name \"mid\[0\]\" in design." {  } { { "E:/毕设资料/程序/仿真/UART/UART.vwf" "" { Waveform "E:/毕设资料/程序/仿真/UART/UART.vwf" "mid\[0\]" "0 ps" "0 ps" "" } }  } 0 0 "Ignored node in vector source file. Can't find corresponding node name \"%1!s!\" in design." 0 0}
{ "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_FOUND" "" "Info: Inverted registers were found during simulation" { { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|UART\|txd:inst1\|txds " "Info: Register: \|UART\|txd:inst1\|txds" {  } {  } 0 0 "Register: %1!s!" 0 0}  } {  } 0 0 "Inverted registers were found during simulation" 0 0}
{ "Info" "IEDS_MAX_TRANSITION_COUNT" "" "Info: Option to preserve fewer signal transitions to reduce memory requirements is enabled" { { "Info" "IEDS_MAX_TRANSITION_COUNT_EXP" "" "Info: Simulation has been partitioned into sub-simulations according to the maximum transition count determined by the engine. Transitions from memory will be flushed out to disk at the end of each sub-simulation to reduce memory requirements." {  } {  } 0 0 "Simulation has been partitioned into sub-simulations according to the maximum transition count determined by the engine. Transitions from memory will be flushed out to disk at the end of each sub-simulation to reduce memory requirements." 0 0}  } {  } 0 0 "Option to preserve fewer signal transitions to reduce memory requirements is enabled" 0 0}
{ "Info" "IEDS_SUB_SIMULATION_COUNT" "1 " "Info: Simulation partitioned into 1 sub-simulations" {  } {  } 0 0 "Simulation partitioned into %1!d! sub-simulations" 0 0}
{ "Info" "ISIM_SIM_SIMULATION_COVERAGE" "     30.45 % " "Info: Simulation coverage is      30.45 %" {  } {  } 0 0 "Simulation coverage is %1!s!" 0 0}
{ "Info" "ISIM_SIM_NUMBER_OF_TRANSITION" "1385041 " "Info: Number of transitions in simulation is 1385041" {  } {  } 0 0 "Number of transitions in simulation is %1!s!" 0 0}
{ "Info" "ISDB_SDB_PROMOTE_WRITE_BINARY_VECTOR" "UART.vwf " "Info: Vector file UART.vwf is saved in VWF text format. You can compress it into CVWF format in order to reduce file size. For more details please refer to the Quartus II Help." {  } {  } 0 0 "Vector file %1!s! is saved in VWF text format. You can compress it into CVWF format in order to reduce file size. For more details please refer to the Quartus II Help." 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Simulator 0 s 8 s Quartus II " "Info: Quartus II Simulator was successful. 0 errors, 8 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "89 " "Info: Allocated 89 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Fri Aug 10 08:27:31 2007 " "Info: Processing ended: Fri Aug 10 08:27:31 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:01:35 " "Info: Elapsed time: 00:01:35" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}