📄 uart.sim.rpt
字号:
; |UART|fre:inst4|Add0~497 ; |UART|fre:inst4|Add0~498 ; cout ;
; |UART|fre:inst4|Add0~499 ; |UART|fre:inst4|Add0~499 ; combout ;
; |UART|fre:inst4|Add0~499 ; |UART|fre:inst4|Add0~500 ; cout0 ;
; |UART|fre:inst4|Add0~499 ; |UART|fre:inst4|Add0~500COUT1 ; cout1 ;
; |UART|fre:inst4|Add0~501 ; |UART|fre:inst4|Add0~501 ; combout ;
; |UART|fre:inst4|Add0~501 ; |UART|fre:inst4|Add0~502 ; cout0 ;
; |UART|fre:inst4|Add0~501 ; |UART|fre:inst4|Add0~502COUT1 ; cout1 ;
; |UART|fre:inst4|Add0~503 ; |UART|fre:inst4|Add0~503 ; combout ;
; |UART|fre:inst4|Add0~503 ; |UART|fre:inst4|Add0~504 ; cout0 ;
; |UART|fre:inst4|Add0~503 ; |UART|fre:inst4|Add0~504COUT1 ; cout1 ;
; |UART|fre:inst4|Add0~505 ; |UART|fre:inst4|Add0~505 ; combout ;
; |UART|fre:inst4|Add0~505 ; |UART|fre:inst4|Add0~506 ; cout0 ;
; |UART|fre:inst4|Add0~505 ; |UART|fre:inst4|Add0~506COUT1 ; cout1 ;
; |UART|fre:inst4|Add0~507 ; |UART|fre:inst4|Add0~507 ; combout ;
; |UART|fre:inst4|Add0~507 ; |UART|fre:inst4|Add0~508 ; cout ;
; |UART|fre:inst4|Add0~509 ; |UART|fre:inst4|Add0~509 ; combout ;
; |UART|fre:inst4|Add0~509 ; |UART|fre:inst4|Add0~510 ; cout0 ;
; |UART|fre:inst4|Add0~509 ; |UART|fre:inst4|Add0~510COUT1 ; cout1 ;
; |UART|fre:inst4|Add0~511 ; |UART|fre:inst4|Add0~511 ; combout ;
; |UART|fre:inst4|Add0~511 ; |UART|fre:inst4|Add0~512 ; cout0 ;
; |UART|fre:inst4|Add0~511 ; |UART|fre:inst4|Add0~512COUT1 ; cout1 ;
; |UART|fre:inst4|Add0~513 ; |UART|fre:inst4|Add0~513 ; combout ;
; |UART|fre:inst4|Add0~513 ; |UART|fre:inst4|Add0~514 ; cout0 ;
; |UART|fre:inst4|Add0~513 ; |UART|fre:inst4|Add0~514COUT1 ; cout1 ;
; |UART|fre:inst4|Add0~515 ; |UART|fre:inst4|Add0~515 ; combout ;
; |UART|fre:inst4|Add0~515 ; |UART|fre:inst4|Add0~516 ; cout0 ;
; |UART|fre:inst4|Add0~515 ; |UART|fre:inst4|Add0~516COUT1 ; cout1 ;
; |UART|fre:inst4|Add0~517 ; |UART|fre:inst4|Add0~517 ; combout ;
; |UART|fre:inst4|Add0~517 ; |UART|fre:inst4|Add0~518 ; cout ;
; |UART|fre:inst4|Add0~519 ; |UART|fre:inst4|Add0~519 ; combout ;
; |UART|fre:inst4|Add0~519 ; |UART|fre:inst4|Add0~520 ; cout0 ;
; |UART|fre:inst4|Add0~519 ; |UART|fre:inst4|Add0~520COUT1 ; cout1 ;
; |UART|fre:inst4|Add0~521 ; |UART|fre:inst4|Add0~521 ; combout ;
; |UART|fre:inst4|Add0~521 ; |UART|fre:inst4|Add0~522 ; cout0 ;
; |UART|fre:inst4|Add0~521 ; |UART|fre:inst4|Add0~522COUT1 ; cout1 ;
; |UART|fre:inst4|Add0~523 ; |UART|fre:inst4|Add0~524 ; cout0 ;
; |UART|fre:inst4|Add0~525 ; |UART|fre:inst4|Add0~526 ; cout0 ;
; |UART|fre:inst4|Add0~527 ; |UART|fre:inst4|Add0~528 ; cout0 ;
; |UART|fre:inst4|Add0~527 ; |UART|fre:inst4|Add0~528COUT1 ; cout1 ;
; |UART|fre:inst4|Add0~529 ; |UART|fre:inst4|Add0~529 ; combout ;
; |UART|fre:inst4|Add0~533 ; |UART|fre:inst4|Add0~534 ; cout0 ;
; |UART|fre:inst4|Add0~535 ; |UART|fre:inst4|Add0~536COUT1 ; cout1 ;
; |UART|fre:inst4|Add0~539 ; |UART|fre:inst4|Add0~540 ; cout0 ;
; |UART|rxd:inst|rbuf[4] ; |UART|rxd:inst|rbuf[4] ; regout ;
; |UART|rxd:inst|rbuf[7] ; |UART|rxd:inst|rbuf[7] ; regout ;
; |UART|rxd:inst|rbuf[0] ; |UART|rxd:inst|rbuf[0] ; regout ;
; |UART|rxd:inst|rbuf[3] ; |UART|rxd:inst|rbuf[3] ; regout ;
; |UART|txd:inst1|Equal1~356 ; |UART|txd:inst1|Equal1~356 ; combout ;
; |UART|txd:inst1|Equal1~357 ; |UART|txd:inst1|Equal1~357 ; combout ;
; |UART|txd:inst1|Equal1~358 ; |UART|txd:inst1|Equal1~358 ; combout ;
; |UART|txd:inst1|Equal1~360 ; |UART|txd:inst1|Equal1~360 ; combout ;
; |UART|txd:inst1|Equal1~361 ; |UART|txd:inst1|Equal1~361 ; combout ;
; |UART|txd:inst1|Equal1~362 ; |UART|txd:inst1|Equal1~362 ; combout ;
; |UART|txd:inst1|Equal1~363 ; |UART|txd:inst1|Equal1~363 ; combout ;
; |UART|txd:inst1|Equal1~364 ; |UART|txd:inst1|Equal1~364 ; combout ;
; |UART|rxd:inst|\pro2:rbufs[5] ; |UART|rxd:inst|\pro2:rbufs[5] ; regout ;
; |UART|rxd:inst|\pro2:rbufs[6] ; |UART|rxd:inst|\pro2:rbufs[6] ; regout ;
; |UART|rxd:inst|\pro2:rbufs[4] ; |UART|rxd:inst|\pro2:rbufs[4] ; regout ;
; |UART|rxd:inst|\pro2:rbufs[7] ; |UART|rxd:inst|\pro2:rbufs[7] ; regout ;
; |UART|rxd:inst|\pro2:rbufs[1] ; |UART|rxd:inst|\pro2:rbufs[1] ; regout ;
; |UART|fre:inst4|count[29] ; |UART|fre:inst4|count[29] ; regout ;
; |UART|fre:inst4|count[30] ; |UART|fre:inst4|Equal0~299 ; combout ;
; |UART|fre:inst4|count[30] ; |UART|fre:inst4|count[30] ; regout ;
; |UART|fre:inst4|count[25] ; |UART|fre:inst4|count[25] ; regout ;
; |UART|fre:inst4|count[24] ; |UART|fre:inst4|count[24] ; regout ;
; |UART|fre:inst4|count[23] ; |UART|fre:inst4|count[23] ; regout ;
; |UART|fre:inst4|count[26] ; |UART|fre:inst4|Equal0~300 ; combout ;
; |UART|fre:inst4|count[26] ; |UART|fre:inst4|count[26] ; regout ;
; |UART|fre:inst4|count[27] ; |UART|fre:inst4|count[27] ; regout ;
; |UART|fre:inst4|count[28] ; |UART|fre:inst4|Equal0~301 ; combout ;
; |UART|fre:inst4|count[28] ; |UART|fre:inst4|count[28] ; regout ;
; |UART|fre:inst4|count[21] ; |UART|fre:inst4|count[21] ; regout ;
; |UART|fre:inst4|count[20] ; |UART|fre:inst4|count[20] ; regout ;
; |UART|fre:inst4|count[19] ; |UART|fre:inst4|count[19] ; regout ;
; |UART|fre:inst4|count[22] ; |UART|fre:inst4|Equal0~302 ; combout ;
; |UART|fre:inst4|count[22] ; |UART|fre:inst4|count[22] ; regout ;
; |UART|fre:inst4|count[17] ; |UART|fre:inst4|count[17] ; regout ;
; |UART|fre:inst4|count[16] ; |UART|fre:inst4|count[16] ; regout ;
; |UART|fre:inst4|count[15] ; |UART|fre:inst4|count[15] ; regout ;
; |UART|fre:inst4|count[18] ; |UART|fre:inst4|Equal0~303 ; combout ;
; |UART|fre:inst4|count[18] ; |UART|fre:inst4|count[18] ; regout ;
; |UART|fre:inst4|count[13] ; |UART|fre:inst4|count[13] ; regout ;
; |UART|fre:inst4|count[12] ; |UART|fre:inst4|count[12] ; regout ;
; |UART|fre:inst4|count[11] ; |UART|fre:inst4|count[11] ; regout ;
; |UART|fre:inst4|count[14] ; |UART|fre:inst4|Equal0~304 ; combout ;
; |UART|fre:inst4|count[14] ; |UART|fre:inst4|count[14] ; regout ;
; |UART|fre:inst4|count[9] ; |UART|fre:inst4|count[9] ; regout ;
; |UART|fre:inst4|count[8] ; |UART|fre:inst4|count[8] ; regout ;
; |UART|fre:inst4|count[10] ; |UART|fre:inst4|Equal0~305 ; combout ;
; |UART|fre:inst4|count[10] ; |UART|fre:inst4|count[10] ; regout ;
; |UART|fre:inst4|Equal0~306 ; |UART|fre:inst4|Equal0~306 ; combout ;
; |UART|fre:inst4|count[31] ; |UART|fre:inst4|count[31] ; regout ;
; |UART|rxd:inst|Equal2~360 ; |UART|rxd:inst|Equal2~360 ; combout ;
; |UART|rxd:inst|Equal2~361 ; |UART|rxd:inst|Equal2~361 ; combout ;
; |UART|rxd:inst|Equal2~362 ; |UART|rxd:inst|Equal2~362 ; combout ;
; |UART|rxd:inst|Equal2~364 ; |UART|rxd:inst|Equal2~364 ; combout ;
; |UART|rxd:inst|Equal2~365 ; |UART|rxd:inst|Equal2~365 ; combout ;
; |UART|rxd:inst|Equal2~366 ; |UART|rxd:inst|Equal2~366 ; combout ;
; |UART|rxd:inst|Equal2~367 ; |UART|rxd:inst|Equal2~367 ; combout ;
; |UART|rxd:inst|Equal2~368 ; |UART|rxd:inst|Equal2~368 ; combout ;
; |UART|reset ; |UART|reset ; combout ;
+-------------------------------+--------------------------------------+------------------+
+---------------------+
; Simulator INI Usage ;
+--------+------------+
; Option ; Usage ;
+--------+------------+
+--------------------+
; Simulator Messages ;
+--------------------+
Info: *******************************************************************
Info: Running Quartus II Simulator
Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
Info: Processing started: Fri Aug 10 08:25:56 2007
Info: Command: quartus_sim --read_settings_files=on --write_settings_files=off UART -c UART
Info: Using vector source file "E:/毕设资料/程序/仿真/UART/UART.vwf"
Info: Overwriting simulation input file with simulation results
Info: A backup of UART.vwf called UART.sim_ori.vwf has been created in the db folder
Warning: Ignored node in vector source file. Can't find corresponding node name "mid[7]" in design.
Warning: Ignored node in vector source file. Can't find corresponding node name "mid[6]" in design.
Warning: Ignored node in vector source file. Can't find corresponding node name "mid[5]" in design.
Warning: Ignored node in vector source file. Can't find corresponding node name "mid[4]" in design.
Warning: Ignored node in vector source file. Can't find corresponding node name "mid[3]" in design.
Warning: Ignored node in vector source file. Can't find corresponding node name "mid[2]" in design.
Warning: Ignored node in vector source file. Can't find corresponding node name "mid[1]" in design.
Warning: Ignored node in vector source file. Can't find corresponding node name "mid[0]" in design.
Info: Inverted registers were found during simulation
Info: Register: |UART|txd:inst1|txds
Info: Option to preserve fewer signal transitions to reduce memory requirements is enabled
Info: Simulation has been partitioned into sub-simulations according to the maximum transition count determined by the engine. Transitions from memory will be flushed out to disk at the end of each sub-simulation to reduce memory requirements.
Info: Simulation partitioned into 1 sub-simulations
Info: Simulation coverage is 30.45 %
Info: Number of transitions in simulation is 1385041
Info: Vector file UART.vwf is saved in VWF text format. You can compress it into CVWF format in order to reduce file size. For more details please refer to the Quartus II Help.
Info: Quartus II Simulator was successful. 0 errors, 8 warnings
Info: Allocated 89 megabytes of memory during processing
Info: Processing ended: Fri Aug 10 08:27:31 2007
Info: Elapsed time: 00:01:35
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -