uart.fit.smsg

基于FPGA的UART实现 用VHDL编程

Info: *******************************************************************
Info: Running Quartus II Fitter
    Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
    Info: Processing started: Fri Aug 10 08:20:10 2007
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off UART -c UART
Info: Selected device EP1C3T144C8 for design "UART"
Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Info: The Fitter has identified 1 logical partitions of which 0 have a previous placement to use
    Info: Previous placement does not exist for 240 of 240 atoms in partition Top
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
    Info: Device EP1C6T144C8 is compatible
Info: Fitter converted 2 user pins into dedicated programming pins
    Info: Pin ~nCSO~ is reserved at location 12
    Info: Pin ~ASDO~ is reserved at location 25
Info: Fitter is using the Classic Timing Analyzer
Info: Detected fmax, tsu, tco, and/or tpd requirements -- optimizing circuit to achieve only the specified requirements
Info: Completed User Assigned Global Signals Promotion Operation
Info: DQS I/O pins require 0 global routing resources
Info: Automatically promoted signal "clk" to use Global clock in PIN 17
Info: Automatically promoted some destinations of signal "fre:inst4|bclk" to use Global clock
    Info: Destination "fre:inst4|bclk" may be non-global or may not use global clock
Info: Automatically promoted some destinations of signal "reset" to use Global clock
    Info: Destination "rxd:inst|r_ready" may be non-global or may not use global clock
    Info: Destination "txd:inst1|xcnt16[4]~283" may be non-global or may not use global clock
    Info: Destination "txd:inst1|xbitcnt[0]~660" may be non-global or may not use global clock
    Info: Destination "rxd:inst|rbuf[7]~279" may be non-global or may not use global clock
    Info: Destination "rxd:inst|Decoder0~104" may be non-global or may not use global clock
    Info: Destination "rxd:inst|\pro2:rcnt[0]~55" may be non-global or may not use global clock
Info: Pin "reset" drives global clock, but is not placed in a dedicated clock pin position
Info: Completed Auto Global Promotion Operation
Info: Starting register packing
Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option
Info: Finished moving registers into I/O cells, LUTs, and RAM blocks
Info: Finished register packing: elapsed time is 00:00:00
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Fitter placement operations ending: elapsed time is 00:00:00
Info: Estimated most critical path is register to register delay of 6.337 ns
    Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X20_Y10; Fanout = 6; REG Node = 'txd:inst1|xbitcnt[0]'
    Info: 2: + IC(1.363 ns) + CELL(0.442 ns) = 1.805 ns; Loc. = LAB_X18_Y9; Fanout = 1; COMB Node = 'txd:inst1|Mux0~33'
    Info: 3: + IC(0.117 ns) + CELL(0.590 ns) = 2.512 ns; Loc. = LAB_X18_Y9; Fanout = 1; COMB Node = 'txd:inst1|Mux0~34'
    Info: 4: + IC(1.384 ns) + CELL(0.292 ns) = 4.188 ns; Loc. = LAB_X20_Y10; Fanout = 1; COMB Node = 'txd:inst1|Selector9~254'
    Info: 5: + IC(0.540 ns) + CELL(0.114 ns) = 4.842 ns; Loc. = LAB_X20_Y10; Fanout = 1; COMB Node = 'txd:inst1|Selector9~255'
    Info: 6: + IC(0.757 ns) + CELL(0.738 ns) = 6.337 ns; Loc. = LAB_X21_Y11; Fanout = 2; REG Node = 'txd:inst1|txds'
    Info: Total cell delay = 2.176 ns ( 34.34 % )
    Info: Total interconnect delay = 4.161 ns ( 65.66 % )
Info: Fitter routing operations beginning
Info: Average interconnect usage is 1% of the available device resources. Peak interconnect usage is 1%
    Info: The peak interconnect region extends from location X14_Y0 to location X27_Y14
Info: Fitter routing operations ending: elapsed time is 00:00:00
Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time.
    Info: Optimizations that may affect the design's routability were skipped
    Info: Optimizations that may affect the design's timing were skipped
Info: Completed Fixed Delay Chain Operation
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Info: Completed Auto Delay Chain Operation
Info: Quartus II Fitter was successful. 0 errors, 0 warnings
    Info: Allocated 162 megabytes of memory during processing
    Info: Processing ended: Fri Aug 10 08:20:18 2007
    Info: Elapsed time: 00:00:08