uart.fit.rpt

基于FPGA的UART实现 用VHDL编程

+---------------------------------------------------------------------------+
; LAB Logic Elements                                                        ;
+--------------------------------------------+------------------------------+
; Number of Logic Elements  (Average = 5.95) ; Number of LABs  (Total = 37) ;
+--------------------------------------------+------------------------------+
; 1                                          ; 13                           ;
; 2                                          ; 0                            ;
; 3                                          ; 1                            ;
; 4                                          ; 3                            ;
; 5                                          ; 0                            ;
; 6                                          ; 0                            ;
; 7                                          ; 2                            ;
; 8                                          ; 1                            ;
; 9                                          ; 0                            ;
; 10                                         ; 17                           ;
+--------------------------------------------+------------------------------+


+-------------------------------------------------------------------+
; LAB-wide Signals                                                  ;
+------------------------------------+------------------------------+
; LAB-wide Signals  (Average = 1.22) ; Number of LABs  (Total = 37) ;
+------------------------------------+------------------------------+
; 1 Async. clear                     ; 7                            ;
; 1 Clock                            ; 23                           ;
; 1 Clock enable                     ; 7                            ;
; 1 Sync. clear                      ; 8                            ;
+------------------------------------+------------------------------+


+----------------------------------------------------------------------------+
; LAB Signals Sourced                                                        ;
+---------------------------------------------+------------------------------+
; Number of Signals Sourced  (Average = 6.27) ; Number of LABs  (Total = 37) ;
+---------------------------------------------+------------------------------+
; 0                                           ; 0                            ;
; 1                                           ; 13                           ;
; 2                                           ; 0                            ;
; 3                                           ; 1                            ;
; 4                                           ; 0                            ;
; 5                                           ; 3                            ;
; 6                                           ; 0                            ;
; 7                                           ; 0                            ;
; 8                                           ; 1                            ;
; 9                                           ; 1                            ;
; 10                                          ; 16                           ;
; 11                                          ; 1                            ;
; 12                                          ; 0                            ;
; 13                                          ; 1                            ;
+---------------------------------------------+------------------------------+


+--------------------------------------------------------------------------------+
; LAB Signals Sourced Out                                                        ;
+-------------------------------------------------+------------------------------+
; Number of Signals Sourced Out  (Average = 4.76) ; Number of LABs  (Total = 37) ;
+-------------------------------------------------+------------------------------+
; 0                                               ; 0                            ;
; 1                                               ; 13                           ;
; 2                                               ; 2                            ;
; 3                                               ; 1                            ;
; 4                                               ; 0                            ;
; 5                                               ; 8                            ;
; 6                                               ; 0                            ;
; 7                                               ; 2                            ;
; 8                                               ; 3                            ;
; 9                                               ; 2                            ;
; 10                                              ; 6                            ;
+-------------------------------------------------+------------------------------+


+----------------------------------------------------------------------------+
; LAB Distinct Inputs                                                        ;
+---------------------------------------------+------------------------------+
; Number of Distinct Inputs  (Average = 6.62) ; Number of LABs  (Total = 37) ;
+---------------------------------------------+------------------------------+
; 0                                           ; 0                            ;
; 1                                           ; 0                            ;
; 2                                           ; 2                            ;
; 3                                           ; 0                            ;
; 4                                           ; 16                           ;
; 5                                           ; 3                            ;
; 6                                           ; 1                            ;
; 7                                           ; 2                            ;
; 8                                           ; 2                            ;
; 9                                           ; 1                            ;
; 10                                          ; 1                            ;
; 11                                          ; 5                            ;
; 12                                          ; 2                            ;
; 13                                          ; 0                            ;
; 14                                          ; 2                            ;
+---------------------------------------------+------------------------------+


+--------------------------------------------------------------------+
; Fitter Device Options                                              ;
+----------------------------------------------+---------------------+
; Option                                       ; Setting             ;
+----------------------------------------------+---------------------+
; Enable user-supplied start-up clock (CLKUSR) ; Off                 ;
; Enable device-wide reset (DEV_CLRn)          ; Off                 ;
; Enable device-wide output enable (DEV_OE)    ; Off                 ;
; Enable INIT_DONE output                      ; Off                 ;
; Configuration scheme                         ; Active Serial       ;
; Error detection CRC                          ; Off                 ;
; Reserve all unused pins                      ; As input tri-stated ;
; Base pin-out file on sameframe device        ; Off                 ;
+----------------------------------------------+---------------------+


+-----------------+
; Fitter Messages ;
+-----------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
    Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
    Info: Processing started: Fri Aug 10 08:20:10 2007
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off UART -c UART
Info: Selected device EP1C3T144C8 for design "UART"
Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Info: The Fitter has identified 1 logical partitions of which 0 have a previous placement to use
    Info: Previous placement does not exist for 240 of 240 atoms in partition Top
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
    Info: Device EP1C6T144C8 is compatible
Info: Fitter converted 2 user pins into dedicated programming pins
    Info: Pin ~nCSO~ is reserved at location 12
    Info: Pin ~ASDO~ is reserved at location 25
Info: Fitter is using the Classic Timing Analyzer
Info: Detected fmax, tsu, tco, and/or tpd requirements -- optimizing circuit to achieve only the specified requirements
Info: Completed User Assigned Global Signals Promotion Operation
Info: DQS I/O pins require 0 global routing resources
Info: Automatically promoted signal "clk" to use Global clock in PIN 17
Info: Automatically promoted some destinations of signal "fre:inst4|bclk" to use Global clock
    Info: Destination "fre:inst4|bclk" may be non-global or may not use global clock
Info: Auto