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📄 uart.map.rpt

📁 基于FPGA的UART实现 用VHDL编程
💻 RPT
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; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                    ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
; |UART                      ; 237 (0)     ; 134          ; 0           ; 0    ; 0            ; 103 (0)      ; 36 (0)            ; 98 (0)           ; 101 (0)         ; 0 (0)      ; |UART               ;
;    |fre:inst4|             ; 79 (79)     ; 33           ; 0           ; 0    ; 0            ; 46 (46)      ; 28 (28)           ; 5 (5)            ; 32 (32)         ; 0 (0)      ; |UART|fre:inst4     ;
;    |rxd:inst|              ; 85 (85)     ; 58           ; 0           ; 0    ; 0            ; 27 (27)      ; 8 (8)             ; 50 (50)          ; 32 (32)         ; 0 (0)      ; |UART|rxd:inst      ;
;    |txd:inst1|             ; 73 (73)     ; 43           ; 0           ; 0    ; 0            ; 30 (30)      ; 0 (0)             ; 43 (43)          ; 37 (37)         ; 0 (0)      ; |UART|txd:inst1     ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


Encoding Type:  One-Hot
+------------------------------------------------------------------------------------------------+
; State Machine - |UART|rxd:inst|state                                                           ;
+----------------+--------------+----------------+--------------+----------------+---------------+
; Name           ; state.r_stop ; state.r_sample ; state.r_wait ; state.r_center ; state.r_start ;
+----------------+--------------+----------------+--------------+----------------+---------------+
; state.r_start  ; 0            ; 0              ; 0            ; 0              ; 0             ;
; state.r_center ; 0            ; 0              ; 0            ; 1              ; 1             ;
; state.r_wait   ; 0            ; 0              ; 1            ; 0              ; 1             ;
; state.r_sample ; 0            ; 1              ; 0            ; 0              ; 1             ;
; state.r_stop   ; 1            ; 0              ; 0            ; 0              ; 1             ;
+----------------+--------------+----------------+--------------+----------------+---------------+


Encoding Type:  One-Hot
+--------------------------------------------------------------------------------------------+
; State Machine - |UART|txd:inst1|state                                                      ;
+---------------+--------------+---------------+--------------+---------------+--------------+
; Name          ; state.x_stop ; state.x_shift ; state.x_wait ; state.x_start ; state.x_idle ;
+---------------+--------------+---------------+--------------+---------------+--------------+
; state.x_idle  ; 0            ; 0             ; 0            ; 0             ; 0            ;
; state.x_start ; 0            ; 0             ; 0            ; 1             ; 1            ;
; state.x_wait  ; 0            ; 0             ; 1            ; 0             ; 1            ;
; state.x_shift ; 0            ; 1             ; 0            ; 0             ; 1            ;
; state.x_stop  ; 1            ; 0             ; 0            ; 0             ; 1            ;
+---------------+--------------+---------------+--------------+---------------+--------------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 134   ;
; Number of registers using Synchronous Clear  ; 69    ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 15    ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 82    ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+--------------------------------------------------+
; Inverted Register Statistics                     ;
+----------------------------------------+---------+
; Inverted Register                      ; Fan out ;
+----------------------------------------+---------+
; txd:inst1|txds                         ; 2       ;
; Total number of inverted registers = 1 ;         ;
+----------------------------------------+---------+


+---------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                              ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output    ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-------------------------------+
; 4:1                ; 32 bits   ; 64 LEs        ; 32 LEs               ; 32 LEs                 ; Yes        ; |UART|rxd:inst|\pro2:rcnt[6]  ;
; 5:1                ; 32 bits   ; 96 LEs        ; 32 LEs               ; 64 LEs                 ; Yes        ; |UART|txd:inst1|xbitcnt[13]   ;
; 6:1                ; 4 bits    ; 16 LEs        ; 4 LEs                ; 12 LEs                 ; Yes        ; |UART|rxd:inst|\pro2:count[0] ;
; 7:1                ; 5 bits    ; 20 LEs        ; 5 LEs                ; 15 LEs                 ; Yes        ; |UART|txd:inst1|xcnt16[4]     ;
; 3:1                ; 2 bits    ; 4 LEs         ; 2 LEs                ; 2 LEs                  ; No         ; |UART|rxd:inst|state~7        ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-------------------------------+


+--------------------------------------------------------+
; Parameter Settings for User Entity Instance: txd:inst1 ;
+----------------+-------+-------------------------------+
; Parameter Name ; Value ; Type                          ;
+----------------+-------+-------------------------------+
; framlent       ; 8     ; Untyped                       ;
+----------------+-------+-------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------+
; Parameter Settings for User Entity Instance: fre:inst4 ;
+----------------+-------+-------------------------------+
; Parameter Name ; Value ; Type                          ;
+----------------+-------+-------------------------------+
; n              ; 156   ; Untyped                       ;
+----------------+-------+-------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------+
; Parameter Settings for User Entity Instance: rxd:inst ;
+----------------+-------+------------------------------+
; Parameter Name ; Value ; Type                         ;
+----------------+-------+------------------------------+
; framlenr       ; 8     ; Untyped                      ;
+----------------+-------+------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
    Info: Processing started: Fri Aug 10 08:19:55 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off UART -c UART
Info: Found 2 design units, including 1 entities, in source file rxd.vhd
    Info: Found design unit 1: rxd-Behavioral
    Info: Found entity 1: rxd
Info: Found 2 design units, including 1 entities, in source file txd.vhd
    Info: Found design unit 1: txd-Behavioral
    Info: Found entity 1: txd
Info: Found 2 design units, including 1 entities, in source file fre.vhd
    Info: Found design unit 1: fre-Behavioral
    Info: Found entity 1: fre
Info: Found 1 design units, including 1 entities, in source file UART.bdf
    Info: Found entity 1: UART
Info: Elaborating entity "UART" for the top level hierarchy
Info: Elaborating entity "txd" for hierarchy "txd:inst1"
Info: Elaborating entity "fre" for hierarchy "fre:inst4"
Info: Elaborating entity "rxd" for hierarchy "rxd:inst"
Info: State machine "|UART|rxd:inst|state" contains 5 states
Info: State machine "|UART|txd:inst1|state" contains 5 states
Info: Selected Auto state machine encoding method for state machine "|UART|rxd:inst|state"
Info: Encoding result for state machine "|UART|rxd:inst|state"
    Info: Completed encoding using 5 state bits
        Info: Encoded state bit "rxd:inst|state.r_stop"
        Info: Encoded state bit "rxd:inst|state.r_sample"
        Info: Encoded state bit "rxd:inst|state.r_wait"
        Info: Encoded state bit "rxd:inst|state.r_center"
        Info: Encoded state bit "rxd:inst|state.r_start"
    Info: State "|UART|rxd:inst|state.r_start" uses code string "00000"
    Info: State "|UART|rxd:inst|state.r_center" uses code string "00011"
    Info: State "|UART|rxd:inst|state.r_wait" uses code string "00101"
    Info: State "|UART|rxd:inst|state.r_sample" uses code string "01001"
    Info: State "|UART|rxd:inst|state.r_stop" uses code string "10001"
Info: Selected Auto state machine encoding method for state machine "|UART|txd:inst1|state"
Info: Encoding result for state machine "|UART|txd:inst1|state"
    Info: Completed encoding using 5 state bits
        Info: Encoded state bit "txd:inst1|state.x_stop"
        Info: Encoded state bit "txd:inst1|state.x_shift"
        Info: Encoded state bit "txd:inst1|state.x_wait"
        Info: Encoded state bit "txd:inst1|state.x_start"
        Info: Encoded state bit "txd:inst1|state.x_idle"
    Info: State "|UART|txd:inst1|state.x_idle" uses code string "00000"
    Info: State "|UART|txd:inst1|state.x_start" uses code string "00011"
    Info: State "|UART|txd:inst1|state.x_wait" uses code string "00101"
    Info: State "|UART|txd:inst1|state.x_shift" uses code string "01001"
    Info: State "|UART|txd:inst1|state.x_stop" uses code string "10001"
Info: Registers with preset signals will power-up high
Info: Implemented 241 device resources after synthesis - the final resource count might be different
    Info: Implemented 3 input pins
    Info: Implemented 1 output pins
    Info: Implemented 237 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings
    Info: Allocated 140 megabytes of memory during processing
    Info: Processing ended: Fri Aug 10 08:20:01 2007
    Info: Elapsed time: 00:00:06


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