_primary.vhd

用verilog鉴定10010序列

        g3_time_delay   : integer := 0;
        e0_time_delay   : integer := 0;
        e1_time_delay   : integer := 0;
        e2_time_delay   : integer := 0;
        e3_time_delay   : integer := 0;
        m_time_delay    : integer := 0;
        n_time_delay    : integer := 0;
        extclk3_counter : string  := "e3";
        extclk2_counter : string  := "e2";
        extclk1_counter : string  := "e1";
        extclk0_counter : string  := "e0";
        clk9_counter    : string  := "c9";
        clk8_counter    : string  := "c8";
        clk7_counter    : string  := "c7";
        clk6_counter    : string  := "c6";
        clk5_counter    : string  := "l1";
        clk4_counter    : string  := "l0";
        clk3_counter    : string  := "g3";
        clk2_counter    : string  := "g2";
        clk1_counter    : string  := "g1";
        clk0_counter    : string  := "g0";
        enable0_counter : string  := "l0";
        enable1_counter : string  := "l0";
        charge_pump_current: integer := 2;
        loop_filter_r   : string  := "1.0";
        loop_filter_c   : integer := 5;
        vco_post_scale  : integer := 0;
        vco_frequency_control: string  := "AUTO";
        vco_phase_shift_step: integer := 0;
        lpm_type        : string  := "altpll";
        port_clkena0    : string  := "PORT_CONNECTIVITY";
        port_clkena1    : string  := "PORT_CONNECTIVITY";
        port_clkena2    : string  := "PORT_CONNECTIVITY";
        port_clkena3    : string  := "PORT_CONNECTIVITY";
        port_clkena4    : string  := "PORT_CONNECTIVITY";
        port_clkena5    : string  := "PORT_CONNECTIVITY";
        port_clkena6    : string  := "PORT_CONNECTIVITY";
        port_clkena7    : string  := "PORT_CONNECTIVITY";
        port_clkena8    : string  := "PORT_CONNECTIVITY";
        port_clkena9    : string  := "PORT_CONNECTIVITY";
        port_extclkena0 : string  := "PORT_CONNECTIVITY";
        port_extclkena1 : string  := "PORT_CONNECTIVITY";
        port_extclkena2 : string  := "PORT_CONNECTIVITY";
        port_extclkena3 : string  := "PORT_CONNECTIVITY";
        port_extclk0    : string  := "PORT_CONNECTIVITY";
        port_extclk1    : string  := "PORT_CONNECTIVITY";
        port_extclk2    : string  := "PORT_CONNECTIVITY";
        port_extclk3    : string  := "PORT_CONNECTIVITY";
        port_clk0       : string  := "PORT_CONNECTIVITY";
        port_clk1       : string  := "PORT_CONNECTIVITY";
        port_clk2       : string  := "PORT_CONNECTIVITY";
        port_clk3       : string  := "PORT_CONNECTIVITY";
        port_clk4       : string  := "PORT_CONNECTIVITY";
        port_clk5       : string  := "PORT_CONNECTIVITY";
        port_clk6       : string  := "PORT_CONNECTIVITY";
        port_clk7       : string  := "PORT_CONNECTIVITY";
        port_clk8       : string  := "PORT_CONNECTIVITY";
        port_clk9       : string  := "PORT_CONNECTIVITY";
        port_scandata   : string  := "PORT_CONNECTIVITY";
        port_scandataout: string  := "PORT_CONNECTIVITY";
        port_scandone   : string  := "PORT_CONNECTIVITY";
        port_sclkout1   : string  := "PORT_CONNECTIVITY";
        port_sclkout0   : string  := "PORT_CONNECTIVITY";
        port_clkbad0    : string  := "PORT_CONNECTIVITY";
        port_clkbad1    : string  := "PORT_CONNECTIVITY";
        port_activeclock: string  := "PORT_CONNECTIVITY";
        port_clkloss    : string  := "PORT_CONNECTIVITY";
        port_inclk1     : string  := "PORT_CONNECTIVITY";
        port_inclk0     : string  := "PORT_CONNECTIVITY";
        port_fbin       : string  := "PORT_CONNECTIVITY";
        port_fbout      : string  := "PORT_CONNECTIVITY";
        port_pllena     : string  := "PORT_CONNECTIVITY";
        port_clkswitch  : string  := "PORT_CONNECTIVITY";
        port_areset     : string  := "PORT_CONNECTIVITY";
        port_pfdena     : string  := "PORT_CONNECTIVITY";
        port_scanclk    : string  := "PORT_CONNECTIVITY";
        port_scanaclr   : string  := "PORT_CONNECTIVITY";
        port_scanread   : string  := "PORT_CONNECTIVITY";
        port_scanwrite  : string  := "PORT_CONNECTIVITY";
        port_enable0    : string  := "PORT_CONNECTIVITY";
        port_enable1    : string  := "PORT_CONNECTIVITY";
        port_locked     : string  := "PORT_CONNECTIVITY";
        port_configupdate: string  := "PORT_CONNECTIVITY";
        port_phasecounterselect: string  := "PORT_CONNECTIVITY";
        port_phasedone  : string  := "PORT_CONNECTIVITY";
        port_phasestep  : string  := "PORT_CONNECTIVITY";
        port_phaseupdown: string  := "PORT_CONNECTIVITY";
        port_vcooverrange: string  := "PORT_CONNECTIVITY";
        port_vcounderrange: string  := "PORT_CONNECTIVITY";
        port_scanclkena : string  := "PORT_CONNECTIVITY";
        using_fbmimicbidir_port: string  := "ON";
        c0_high         : integer := 1;
        c1_high         : integer := 1;
        c2_high         : integer := 1;
        c3_high         : integer := 1;
        c4_high         : integer := 1;
        c5_high         : integer := 1;
        c6_high         : integer := 1;
        c7_high         : integer := 1;
        c8_high         : integer := 1;
        c9_high         : integer := 1;
        c0_low          : integer := 1;
        c1_low          : integer := 1;
        c2_low          : integer := 1;
        c3_low          : integer := 1;
        c4_low          : integer := 1;
        c5_low          : integer := 1;
        c6_low          : integer := 1;
        c7_low          : integer := 1;
        c8_low          : integer := 1;
        c9_low          : integer := 1;
        c0_initial      : integer := 1;
        c1_initial      : integer := 1;
        c2_initial      : integer := 1;
        c3_initial      : integer := 1;
        c4_initial      : integer := 1;
        c5_initial      : integer := 1;
        c6_initial      : integer := 1;
        c7_initial      : integer := 1;
        c8_initial      : integer := 1;
        c9_initial      : integer := 1;
        c0_mode         : string  := "bypass";
        c1_mode         : string  := "bypass";
        c2_mode         : string  := "bypass";
        c3_mode         : string  := "bypass";
        c4_mode         : string  := "bypass";
        c5_mode         : string  := "bypass";
        c6_mode         : string  := "bypass";
        c7_mode         : string  := "bypass";
        c8_mode         : string  := "bypass";
        c9_mode         : string  := "bypass";
        c0_ph           : integer := 0;
        c1_ph           : integer := 0;
        c2_ph           : integer := 0;
        c3_ph           : integer := 0;
        c4_ph           : integer := 0;
        c5_ph           : integer := 0;
        c6_ph           : integer := 0;
        c7_ph           : integer := 0;
        c8_ph           : integer := 0;
        c9_ph           : integer := 0;
        c1_use_casc_in  : string  := "off";
        c2_use_casc_in  : string  := "off";
        c3_use_casc_in  : string  := "off";
        c4_use_casc_in  : string  := "off";
        c5_use_casc_in  : string  := "off";
        c6_use_casc_in  : string  := "off";
        c7_use_casc_in  : string  := "off";
        c8_use_casc_in  : string  := "off";
        c9_use_casc_in  : string  := "off";
        m_test_source   : integer := 5;
        c0_test_source  : integer := 5;
        c1_test_source  : integer := 5;
        c2_test_source  : integer := 5;
        c3_test_source  : integer := 5;
        c4_test_source  : integer := 5;
        c5_test_source  : integer := 5;
        c6_test_source  : integer := 5;
        c7_test_source  : integer := 5;
        c8_test_source  : integer := 5;
        c9_test_source  : integer := 5;
        sim_gate_lock_device_behavior: string  := "OFF"
    );
    port(
        inclk           : in     vl_logic_vector(1 downto 0);
        fbin            : in     vl_logic;
        pllena          : in     vl_logic;
        clkswitch       : in     vl_logic;
        areset          : in     vl_logic;
        pfdena          : in     vl_logic;
        clkena          : in     vl_logic_vector(5 downto 0);
        extclkena       : in     vl_logic_vector(3 downto 0);
        scanclk         : in     vl_logic;
        scanaclr        : in     vl_logic;
        scanclkena      : in     vl_logic;
        scanread        : in     vl_logic;
        scanwrite       : in     vl_logic;
        scandata        : in     vl_logic;
        phasecounterselect: in     vl_logic_vector;
        phaseupdown     : in     vl_logic;
        phasestep       : in     vl_logic;
        configupdate    : in     vl_logic;
        fbmimicbidir    : inout  vl_logic;
        clk             : out    vl_logic_vector;
        extclk          : out    vl_logic_vector(3 downto 0);
        clkbad          : out    vl_logic_vector(1 downto 0);
        enable0         : out    vl_logic;
        enable1         : out    vl_logic;
        activeclock     : out    vl_logic;
        clkloss         : out    vl_logic;
        locked          : out    vl_logic;
        scandataout     : out    vl_logic;
        scandone        : out    vl_logic;
        sclkout0        : out    vl_logic;
        sclkout1        : out    vl_logic;
        phasedone       : out    vl_logic;
        vcooverrange    : out    vl_logic;
        vcounderrange   : out    vl_logic;
        fbout           : out    vl_logic
    );
end altpll;