freq_ram_ctrl.map.qmsg

使用VHDL语言描述AD0809芯片功能

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Full Version " "Info: Version 7.2 Build 151 09/26/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun May 18 15:58:50 2008 " "Info: Processing started: Sun May 18 15:58:50 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off freq_ram_ctrl -c freq_ram_ctrl " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off freq_ram_ctrl -c freq_ram_ctrl" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "freq_ram_ctrl.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file freq_ram_ctrl.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 freq_ram_ctrl-freq_ram_ctrl " "Info: Found design unit 1: freq_ram_ctrl-freq_ram_ctrl" {  } { { "freq_ram_ctrl.vhd" "" { Text "D:/new AD/show_port/freq_ram_ctrl/freq_ram_ctrl.vhd" 20 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 freq_ram_ctrl " "Info: Found entity 1: freq_ram_ctrl" {  } { { "freq_ram_ctrl.vhd" "" { Text "D:/new AD/show_port/freq_ram_ctrl/freq_ram_ctrl.vhd" 9 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "freq_ram.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file freq_ram.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 freq_ram-SYN " "Info: Found design unit 1: freq_ram-SYN" {  } { { "freq_ram.vhd" "" { Text "D:/new AD/show_port/freq_ram_ctrl/freq_ram.vhd" 56 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 freq_ram " "Info: Found entity 1: freq_ram" {  } { { "freq_ram.vhd" "" { Text "D:/new AD/show_port/freq_ram_ctrl/freq_ram.vhd" 42 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../show_port_pack.vhd 1 0 " "Info: Found 1 design units, including 0 entities, in source file ../show_port_pack.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 show_port_pack " "Info: Found design unit 1: show_port_pack" {  } { { "../show_port_pack.vhd" "" { Text "D:/new AD/show_port/show_port_pack.vhd" 4 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../divide10_99.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file ../divide10_99.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 divide10_99-SYN " "Info: Found design unit 1: divide10_99-SYN" {  } { { "../divide10_99.vhd" "" { Text "D:/new AD/show_port/divide10_99.vhd" 53 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 divide10_99 " "Info: Found entity 1: divide10_99" {  } { { "../divide10_99.vhd" "" { Text "D:/new AD/show_port/divide10_99.vhd" 42 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../divide10_999.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file ../divide10_999.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 divide10_999-SYN " "Info: Found design unit 1: divide10_999-SYN" {  } { { "../divide10_999.vhd" "" { Text "D:/new AD/show_port/divide10_999.vhd" 53 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 divide10_999 " "Info: Found entity 1: divide10_999" {  } { { "../divide10_999.vhd" "" { Text "D:/new AD/show_port/divide10_999.vhd" 42 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../divide10_9999.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file ../divide10_9999.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 divide10_9999-SYN " "Info: Found design unit 1: divide10_9999-SYN" {  } { { "../divide10_9999.vhd" "" { Text "D:/new AD/show_port/divide10_9999.vhd" 53 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 divide10_9999 " "Info: Found entity 1: divide10_9999" {  } { { "../divide10_9999.vhd" "" { Text "D:/new AD/show_port/divide10_9999.vhd" 42 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "V_freq_pack.vhd 1 0 " "Info: Found 1 design units, including 0 entities, in source file V_freq_pack.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 V_freq_pack " "Info: Found design unit 1: V_freq_pack" {  } { { "V_freq_pack.vhd" "" { Text "D:/new AD/show_port/freq_ram_ctrl/V_freq_pack.vhd" 1 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "freq_ram_ctrl " "Info: Elaborating entity \"freq_ram_ctrl\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "divide10_9999 divide10_9999:divide10_9999a " "Info: Elaborating entity \"divide10_9999\" for hierarchy \"divide10_9999:divide10_9999a\"" {  } { { "freq_ram_ctrl.vhd" "divide10_9999a" { Text "D:/new AD/show_port/freq_ram_ctrl/freq_ram_ctrl.vhd" 46 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../../altera/72/quartus/libraries/megafunctions/lpm_divide.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../../altera/72/quartus/libraries/megafunctions/lpm_divide.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_divide " "Info: Found entity 1: lpm_divide" {  } { { "lpm_divide.tdf" "" { Text "d:/altera/72/quartus/libraries/megafunctions/lpm_divide.tdf" 118 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_divide divide10_9999:divide10_9999a\|lpm_divide:lpm_divide_component " "Info: Elaborating entity \"lpm_divide\" for hierarchy \"divide10_9999:divide10_9999a\|lpm_divide:lpm_divide_component\"" {  } { { "../divide10_9999.vhd" "lpm_divide_component" { Text "D:/new AD/show_port/divide10_9999.vhd" 81 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_ELABORATION_HEADER" "divide10_9999:divide10_9999a\|lpm_divide:lpm_divide_component " "Info: Elaborated megafunction instantiation \"divide10_9999:divide10_9999a\|lpm_divide:lpm_divide_component\"" {  } { { "../divide10_9999.vhd" "" { Text "D:/new AD/show_port/divide10_9999.vhd" 81 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/lpm_divide_tsp.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/lpm_divide_tsp.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_divide_tsp " "Info: Found entity 1: lpm_divide_tsp" {  } { { "db/lpm_divide_tsp.tdf" "" { Text "D:/new AD/show_port/freq_ram_ctrl/db/lpm_divide_tsp.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_divide_tsp divide10_9999:divide10_9999a\|lpm_divide:lpm_divide_component\|lpm_divide_tsp:auto_generated " "Info: Elaborating entity \"lpm_divide_tsp\" for hierarchy \"divide10_9999:divide10_9999a\|lpm_divide:lpm_divide_component\|lpm_divide_tsp:auto_generated\"" {  } { { "lpm_divide.tdf" "auto_generated" { Text "d:/altera/72/quartus/libraries/megafunctions/lpm_divide.tdf" 147 9 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/sign_div_unsign_olh.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/sign_div_unsign_olh.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 sign_div_unsign_olh " "Info: Found entity 1: sign_div_unsign_olh" {  } { { "db/sign_div_unsign_olh.tdf" "" { Text "D:/new AD/show_port/freq_ram_ctrl/db/sign_div_unsign_olh.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sign_div_unsign_olh divide10_9999:divide10_9999a\|lpm_divide:lpm_divide_component\|lpm_divide_tsp:auto_generated\|sign_div_unsign_olh:divider " "Info: Elaborating entity \"sign_div_unsign_olh\" for hierarchy \"divide10_9999:divide10_9999a\|lpm_divide:lpm_divide_component\|lpm_divide_tsp:auto_generated\|sign_div_unsign_olh:divider\"" {  } { { "db/lpm_divide_tsp.tdf" "divider" { Text "D:/new AD/show_port/freq_ram_ctrl/db/lpm_divide_tsp.tdf" 32 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/alt_u_div_i2f.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/alt_u_div_i2f.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 alt_u_div_i2f " "Info: Found entity 1: alt_u_div_i2f" {  } { { "db/alt_u_div_i2f.tdf" "" { Text "D:/new AD/show_port/freq_ram_ctrl/db/alt_u_div_i2f.tdf" 26 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alt_u_div_i2f divide10_9999:divide10_9999a\|lpm_divide:lpm_divide_component\|lpm_divide_tsp:auto_generated\|sign_div_unsign_olh:divider\|alt_u_div_i2f:divider " "Info: Elaborating entity \"alt_u_div_i2f\" for hierarchy \"divide10_9999:divide10_9999a\|lpm_divide:lpm_divide_component\|lpm_divide_tsp:auto_generated\|sign_div_unsign_olh:divider\|alt_u_div_i2f:divider\"" {  } { { "db/sign_div_unsign_olh.tdf" "divider" { Text "D:/new AD/show_port/freq_ram_ctrl/db/sign_div_unsign_olh.tdf" 32 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_lkc.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_lkc.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_lkc " "Info: Found entity 1: add_sub_lkc" {  } { { "db/add_sub_lkc.tdf" "" { Text "D:/new AD/show_port/freq_ram_ctrl/db/add_sub_lkc.tdf" 22 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "add_sub_lkc divide10_9999:divide10_9999a\|lpm_divide:lpm_divide_component\|lpm_divide_tsp:auto_generated\|sign_div_unsign_olh:divider\|alt_u_div_i2f:divider\|add_sub_lkc:add_sub_0 " "Info: Elaborating entity \"add_sub_lkc\" for hierarchy \"divide10_9999:divide10_9999a\|lpm_divide:lpm_divide_component\|lpm_divide_tsp:auto_generated\|sign_div_unsign_olh:divider\|alt_u_div_i2f:divider\|add_sub_lkc:add_sub_0\"" {  } { { "db/alt_u_div_i2f.tdf" "add_sub_0" { Text "D:/new AD/show_port/freq_ram_ctrl/db/alt_u_div_i2f.tdf" 35 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_mkc.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_mkc.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_mkc " "Info: Found entity 1: add_sub_mkc" {  } { { "db/add_sub_mkc.tdf" "" { Text "D:/new AD/show_port/freq_ram_ctrl/db/add_sub_mkc.tdf" 22 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "add_sub_mkc divide10_9999:divide10_9999a\|lpm_divide:lpm_divide_component\|lpm_divide_tsp:auto_generated\|sign_div_unsign_olh:divider\|alt_u_div_i2f:divider\|add_sub_mkc:add_sub_1 " "Info: Elaborating entity \"add_sub_mkc\" for hierarchy \"divide10_9999:divide10_9999a\|lpm_divide:lpm_divide_component\|lpm_divide_tsp:auto_generated\|sign_div_unsign_olh:divider\|alt_u_div_i2f:divider\|add_sub_mkc:add_sub_1\"" {  } { { "db/alt_u_div_i2f.tdf" "add_sub_1" { Text "D:/new AD/show_port/freq_ram_ctrl/db/alt_u_div_i2f.tdf" 36 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "divide10_999 divide10_999:divide10_999a " "Info: Elaborating entity \"divide10_999\" for hierarchy \"divide10_999:divide10_999a\"" {  } { { "freq_ram_ctrl.vhd" "divide10_999a" { Text "D:/new AD/show_port/freq_ram_ctrl/freq_ram_ctrl.vhd" 53 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_divide divide10_999:divide10_999a\|lpm_divide:lpm_divide_component " "Info: Elaborating entity \"lpm_divide\" for hierarchy \"divide10_999:divide10_999a\|lpm_divide:lpm_divide_component\"" {  } { { "../divide10_999.vhd" "lpm_divide_component" { Text "D:/new AD/show_port/divide10_999.vhd" 81 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}