define.v

来自「DDR SDRAM控制器的VHDL源代码」· Verilog 代码 · 共 53 行

`define T_RCD 2   //ras to cas delay, for -8 SDRAM, we need 3 clock cycles for t_rcd

`define DDR_ADDR_MSB           11
`define DDR_DATA_MSB           15
`define SYS_ADDR_MSB           21
`define SYS_DATA_MSB           31
`define U_ADDR_MSB             21
`define U_DATA_MSB             31
`define ROW_ADDR_MSB           11
`define COL_ADDR_MSB           	7
`define ENABLE_MSB           	3

//system commands: sys_cmd[7:1]
`define sys_nop                7'b0000001
`define sys_load_mr            7'b0000010
`define sys_read               7'b0000100
`define sys_write              7'b0001000
`define sys_precharge          7'b0010000
`define sys_refresh            7'b0100000
`define sys_burst_stop         7'b1000000

`define SYS_NOP                1
`define SYS_LOAD_MR            2
`define SYS_READ               3
`define SYS_WRITE              4
`define SYS_PRECHARGE          5
`define SYS_REFRESH            6
`define SYS_BURST_STOP         7

   //controller states
`define CTLR_IDLE              1
`define CTLR_REFRESH           2
`define CTLR_PRECHARGE         3
`define CTLR_LOAD_MR           4
`define CTLR_ACT               5
`define CTLR_ACT_WAIT          6               
`define CTLR_READ              7
`define CTLR_WRITE             8
`define CTLR_READ_WAIT         9
`define CTLR_READ_DATA         10
`define CTLR_WRITE_DATA        11

   //DDR commands
`define DDR_LOAD_MR            3'b000
`define DDR_AUTO_REFRESH       3'b001
`define DDR_PRECHARGE          3'b010
`define DDR_ACT                3'b011
`define DDR_WRITEA             3'b100
`define DDR_READA              3'b101
`define DDR_BURST_STOP         3'b110
`define DDR_NOP                3'b111