prev_cmp_fir_16.qmsg

fir滤波器-verilog

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Full Version " "Info: Version 7.2 Build 151 09/26/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Oct 16 15:04:41 2008 " "Info: Processing started: Thu Oct 16 15:04:41 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off fir_16 -c fir_16 " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off fir_16 -c fir_16" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "fft_16.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file fft_16.v" { { "Info" "ISGN_ENTITY_NAME" "1 fft_16 " "Info: Found entity 1: fft_16" {  } { { "fft_16.v" "" { Text "C:/Documents and Settings/Administrator/桌面/fir_16/fft_16.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "fft_16 " "Info: Elaborating entity \"fft_16\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Warning" "WVRFX_VERI_2106_UNCONVERTED" "OUT1 fft_16.v(11) " "Warning (10858): Verilog HDL warning at fft_16.v(11): object OUT1 used but never assigned" {  } { { "fft_16.v" "" { Text "C:/Documents and Settings/Administrator/桌面/fir_16/fft_16.v" 11 0 0 } }  } 0 10858 "Verilog HDL warning at %2!s!: object %1!s! used but never assigned" 0 0 "" 0}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "STRT1 fft_16.v(11) " "Warning (10036): Verilog HDL or VHDL warning at fft_16.v(11): object \"STRT1\" assigned a value but never read" {  } { { "fft_16.v" "" { Text "C:/Documents and Settings/Administrator/桌面/fir_16/fft_16.v" 11 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "" 0}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "TRANIN_r fft_16.v(17) " "Warning (10036): Verilog HDL or VHDL warning at fft_16.v(17): object \"TRANIN_r\" assigned a value but never read" {  } { { "fft_16.v" "" { Text "C:/Documents and Settings/Administrator/桌面/fir_16/fft_16.v" 17 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "" 0}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "TRANIN_i fft_16.v(17) " "Warning (10036): Verilog HDL or VHDL warning at fft_16.v(17): object \"TRANIN_i\" assigned a value but never read" {  } { { "fft_16.v" "" { Text "C:/Documents and Settings/Administrator/桌面/fir_16/fft_16.v" 17 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "" 0}
{ "Warning" "WVRFX_VERI_2106_UNCONVERTED" "TRANOUT_r fft_16.v(18) " "Warning (10858): Verilog HDL warning at fft_16.v(18): object TRANOUT_r used but never assigned" {  } { { "fft_16.v" "" { Text "C:/Documents and Settings/Administrator/桌面/fir_16/fft_16.v" 18 0 0 } }  } 0 10858 "Verilog HDL warning at %2!s!: object %1!s! used but never assigned" 0 0 "" 0}
{ "Warning" "WVRFX_VERI_2106_UNCONVERTED" "TRANOUT_i fft_16.v(18) " "Warning (10858): Verilog HDL warning at fft_16.v(18): object TRANOUT_i used but never assigned" {  } { { "fft_16.v" "" { Text "C:/Documents and Settings/Administrator/桌面/fir_16/fft_16.v" 18 0 0 } }  } 0 10858 "Verilog HDL warning at %2!s!: object %1!s! used but never assigned" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 5 fft_16.v(102) " "Warning (10230): Verilog HDL assignment warning at fft_16.v(102): truncated value with size 32 to match size of target (5)" {  } { { "fft_16.v" "" { Text "C:/Documents and Settings/Administrator/桌面/fir_16/fft_16.v" 102 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}