fir_16.smp_dump.txt

fir滤波器-verilog

State Machine - |fft_16|state
Name state.Output state.Butfly state.Compute1 state.Compute0 state.Input state.Idle 
state.Idle 0 0 0 0 0 0 
state.Input 0 0 0 0 1 1 
state.Compute0 0 0 0 1 0 1 
state.Compute1 0 0 1 0 0 1 
state.Butfly 0 1 0 0 0 1 
state.Output 1 0 0 0 0 1