prev_cmp_topclock.map.qmsg

VHDL言语实现的24制时钟,可整点报时,还有闹钟等功能.

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 175 11/20/2007 Service Pack 1 SJ Full Version " "Info: Version 7.2 Build 175 11/20/2007 Service Pack 1 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Nov 20 00:05:06 2008 " "Info: Processing started: Thu Nov 20 00:05:06 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off topclock -c topclock " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off topclock -c topclock" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "topclock.vhd 10 5 " "Info: Found 10 design units, including 5 entities, in source file topclock.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 topclock-one " "Info: Found design unit 1: topclock-one" {  } { { "topclock.vhd" "" { Text "D:/c/haoleba/topclock.vhd" 18 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "2 second-behav " "Info: Found design unit 2: second-behav" {  } { { "topclock.vhd" "" { Text "D:/c/haoleba/topclock.vhd" 71 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "3 minute-behav " "Info: Found design unit 3: minute-behav" {  } { { "topclock.vhd" "" { Text "D:/c/haoleba/topclock.vhd" 112 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "4 hour-behav " "Info: Found design unit 4: hour-behav" {  } { { "topclock.vhd" "" { Text "D:/c/haoleba/topclock.vhd" 147 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "5 alar-a " "Info: Found design unit 5: alar-a" {  } { { "topclock.vhd" "" { Text "D:/c/haoleba/topclock.vhd" 181 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 topclock " "Info: Found entity 1: topclock" {  } { { "topclock.vhd" "" { Text "D:/c/haoleba/topclock.vhd" 7 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "2 second " "Info: Found entity 2: second" {  } { { "topclock.vhd" "" { Text "D:/c/haoleba/topclock.vhd" 65 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "3 minute " "Info: Found entity 3: minute" {  } { { "topclock.vhd" "" { Text "D:/c/haoleba/topclock.vhd" 107 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "4 hour " "Info: Found entity 4: hour" {  } { { "topclock.vhd" "" { Text "D:/c/haoleba/topclock.vhd" 143 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "5 alar " "Info: Found entity 5: alar" {  } { { "topclock.vhd" "" { Text "D:/c/haoleba/topclock.vhd" 173 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "topclock " "Info: Elaborating entity \"topclock\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "second second:u1 " "Info: Elaborating entity \"second\" for hierarchy \"second:u1\"" {  } { { "topclock.vhd" "u1" { Text "D:/c/haoleba/topclock.vhd" 52 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "cles topclock.vhd(95) " "Warning (10492): VHDL Process Statement warning at topclock.vhd(95): signal \"cles\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "topclock.vhd" "" { Text "D:/c/haoleba/topclock.vhd" 95 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "minute minute:u2 " "Info: Elaborating entity \"minute\" for hierarchy \"minute:u2\"" {  } { { "topclock.vhd" "u2" { Text "D:/c/haoleba/topclock.vhd" 53 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "clem topclock.vhd(129) " "Warning (10492): VHDL Process Statement warning at topclock.vhd(129): signal \"clem\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "topclock.vhd" "" { Text "D:/c/haoleba/topclock.vhd" 129 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "hour hour:u3 " "Info: Elaborating entity \"hour\" for hierarchy \"hour:u3\"" {  } { { "topclock.vhd" "u3" { Text "D:/c/haoleba/topclock.vhd" 54 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "cleh topclock.vhd(162) " "Warning (10492): VHDL Process Statement warning at topclock.vhd(162): signal \"cleh\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "topclock.vhd" "" { Text "D:/c/haoleba/topclock.vhd" 162 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alar alar:u4 " "Info: Elaborating entity \"alar\" for hierarchy \"alar:u4\"" {  } { { "topclock.vhd" "u4" { Text "D:/c/haoleba/topclock.vhd" 55 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "setm topclock.vhd(188) " "Warning (10492): VHDL Process Statement warning at topclock.vhd(188): signal \"setm\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "topclock.vhd" "" { Text "D:/c/haoleba/topclock.vhd" 188 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "minu1 topclock.vhd(188) " "Warning (10492): VHDL Process Statement warning at topclock.vhd(188): signal \"minu1\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "topclock.vhd" "" { Text "D:/c/haoleba/topclock.vhd" 188 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "seth topclock.vhd(188) " "Warning (10492): VHDL Process Statement warning at topclock.vhd(188): signal \"seth\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "topclock.vhd" "" { Text "D:/c/haoleba/topclock.vhd" 188 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "houu1 topclock.vhd(188) " "Warning (10492): VHDL Process Statement warning at topclock.vhd(188): signal \"houu1\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "topclock.vhd" "" { Text "D:/c/haoleba/topclock.vhd" 188 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "al topclock.vhd(194) " "Warning (10492): VHDL Process Statement warning at topclock.vhd(194): signal \"al\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "topclock.vhd" "" { Text "D:/c/haoleba/topclock.vhd" 194 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "al topclock.vhd(184) " "Warning (10631): VHDL Process Statement warning at topclock.vhd(184): inferring latch(es) for signal or variable \"al\", which holds its previous value in one or more paths through the process" {  } { { "topclock.vhd" "" { Text "D:/c/haoleba/topclock.vhd" 184 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "al topclock.vhd(184) " "Info (10041): Inferred latch for \"al\" at topclock.vhd(184)" {  } { { "topclock.vhd" "" { Text "D:/c/haoleba/topclock.vhd" 184 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "alarm GND " "Warning (13410): Pin \"alarm\" stuck at GND" {  } { { "topclock.vhd" "" { Text "D:/c/haoleba/topclock.vhd" 12 -1 0 } }  } 0 13410 "Pin \"%1!s!\" stuck at %2!s!" 0 0 "" 0}  } {  } 0 0 "Output pins are stuck at VCC or GND" 0 0 "" 0}
{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "12 " "Warning: Design contains 12 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "enable " "Warning (15610): No output dependent on input pin \"enable\"" {  } { { "topclock.vhd" "" { Text "D:/c/haoleba/topclock.vhd" 8 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "setm\[0\] " "Warning (15610): No output dependent on input pin \"setm\[0\]\"" {  } { { "topclock.vhd" "" { Text "D:/c/haoleba/topclock.vhd" 10 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "setm\[1\] " "Warning (15610): No output dependent on input pin \"setm\[1\]\"" {  } { { "topclock.vhd" "" { Text "D:/c/haoleba/topclock.vhd" 10 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "setm\[2\] " "Warning (15610): No output dependent on input pin \"setm\[2\]\"" {  } { { "topclock.vhd" "" { Text "D:/c/haoleba/topclock.vhd" 10 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "setm\[3\] " "Warning (15610): No output dependent on input pin \"setm\[3\]\"" {  } { { "topclock.vhd" "" { Text "D:/c/haoleba/topclock.vhd" 10 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "setm\[4\] " "Warning (15610): No output dependent on input pin \"setm\[4\]\"" {  } { { "topclock.vhd" "" { Text "D:/c/haoleba/topclock.vhd" 10 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "setm\[5\] " "Warning (15610): No output dependent on input pin \"setm\[5\]\"" {  } { { "topclock.vhd" "" { Text "D:/c/haoleba/topclock.vhd" 10 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "seth\[0\] " "Warning (15610): No output dependent on input pin \"seth\[0\]\"" {  } { { "topclock.vhd" "" { Text "D:/c/haoleba/topclock.vhd" 11 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "seth\[1\] " "Warning (15610): No output dependent on input pin \"seth\[1\]\"" {  } { { "topclock.vhd" "" { Text "D:/c/haoleba/topclock.vhd" 11 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "seth\[2\] " "Warning (15610): No output dependent on input pin \"seth\[2\]\"" {  } { { "topclock.vhd" "" { Text "D:/c/haoleba/topclock.vhd" 11 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "seth\[3\] " "Warning (15610): No output dependent on input pin \"seth\[3\]\"" {  } { { "topclock.vhd" "" { Text "D:/c/haoleba/topclock.vhd" 11 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "seth\[4\] " "Warning (15610): No output dependent on input pin \"seth\[4\]\"" {  } { { "topclock.vhd" "" { Text "D:/c/haoleba/topclock.vhd" 11 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0}  } {  } 0 0 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "" 0}
{ "Info" "ICUT_CUT_TM_SUMMARY" "66 " "Info: Implemented 66 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "17 " "Info: Implemented 17 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_OPINS" "19 " "Info: Implemented 19 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_LCELLS" "30 " "Info: Implemented 30 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 24 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 24 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "163 " "Info: Allocated 163 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Thu Nov 20 00:05:09 2008 " "Info: Processing ended: Thu Nov 20 00:05:09 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}