topclock.sim.rpt

VHDL言语实现的24制时钟,可整点报时,还有闹钟等功能.

; |topclock|second:u1|counter[1]~102      ; |topclock|second:u1|counter[1]~102      ; combout          ;
; |topclock|second:u1|counter[1]~102      ; |topclock|second:u1|counter[1]~103      ; cout             ;
; |topclock|second:u1|counter[2]~104      ; |topclock|second:u1|counter[2]~104      ; combout          ;
; |topclock|second:u1|counter[2]~104      ; |topclock|second:u1|counter[2]~105      ; cout             ;
; |topclock|second:u1|counter[3]~106      ; |topclock|second:u1|counter[3]~106      ; combout          ;
; |topclock|second:u1|counter[3]~106      ; |topclock|second:u1|counter[3]~107      ; cout             ;
; |topclock|second:u1|counter[4]~108      ; |topclock|second:u1|counter[4]~108      ; combout          ;
; |topclock|second:u1|counter[4]~108      ; |topclock|second:u1|counter[4]~109      ; cout             ;
; |topclock|second:u1|counter[5]~110      ; |topclock|second:u1|counter[5]~110      ; combout          ;
; |topclock|minute:u2|counter[0]~94       ; |topclock|minute:u2|counter[0]~94       ; combout          ;
; |topclock|minute:u2|counter[0]~94       ; |topclock|minute:u2|counter[0]~95       ; cout             ;
; |topclock|minute:u2|counter[1]~96       ; |topclock|minute:u2|counter[1]~96       ; combout          ;
; |topclock|minute:u2|counter[1]~96       ; |topclock|minute:u2|counter[1]~97       ; cout             ;
; |topclock|minute:u2|counter[2]~98       ; |topclock|minute:u2|counter[2]~98       ; combout          ;
; |topclock|minute:u2|counter[2]~98       ; |topclock|minute:u2|counter[2]~99       ; cout             ;
; |topclock|minute:u2|counter[3]~100      ; |topclock|minute:u2|counter[3]~100      ; combout          ;
; |topclock|minute:u2|counter[3]~100      ; |topclock|minute:u2|counter[3]~101      ; cout             ;
; |topclock|minute:u2|counter[4]~102      ; |topclock|minute:u2|counter[4]~102      ; combout          ;
; |topclock|minute:u2|counter[4]~102      ; |topclock|minute:u2|counter[4]~103      ; cout             ;
; |topclock|minute:u2|counter[5]~104      ; |topclock|minute:u2|counter[5]~104      ; combout          ;
; |topclock|hour:u3|counter[0]~66         ; |topclock|hour:u3|counter[0]~66         ; combout          ;
; |topclock|hour:u3|counter[0]~66         ; |topclock|hour:u3|counter[0]~67         ; cout             ;
; |topclock|hour:u3|counter[1]~68         ; |topclock|hour:u3|counter[1]~68         ; combout          ;
; |topclock|hour:u3|counter[1]~68         ; |topclock|hour:u3|counter[1]~69         ; cout             ;
; |topclock|hour:u3|counter[2]~70         ; |topclock|hour:u3|counter[2]~70         ; combout          ;
; |topclock|hour:u3|counter[2]~70         ; |topclock|hour:u3|counter[2]~71         ; cout             ;
; |topclock|hour:u3|counter[3]~72         ; |topclock|hour:u3|counter[3]~72         ; combout          ;
; |topclock|minute:u2|carry_out1          ; |topclock|minute:u2|carry_out1          ; regout           ;
; |topclock|second:u1|carry_out2          ; |topclock|second:u1|carry_out2          ; regout           ;
; |topclock|baoshi~0                      ; |topclock|baoshi~0                      ; combout          ;
; |topclock|minute:u2|LessThan0~77        ; |topclock|minute:u2|LessThan0~77        ; combout          ;
; |topclock|minute:u2|LessThan0~78        ; |topclock|minute:u2|LessThan0~78        ; combout          ;
; |topclock|second:u1|carry_out1          ; |topclock|second:u1|carry_out1          ; regout           ;
; |topclock|second:u1|LessThan1~93        ; |topclock|second:u1|LessThan1~93        ; combout          ;
; |topclock|second:u1|LessThan1~94        ; |topclock|second:u1|LessThan1~94        ; combout          ;
; |topclock|second:u1|counter[5]~0        ; |topclock|second:u1|counter[5]~0        ; combout          ;
; |topclock|second:u1|LessThan0~72        ; |topclock|second:u1|LessThan0~72        ; combout          ;
; |topclock|minute:u2|counter[5]~0        ; |topclock|minute:u2|counter[5]~0        ; combout          ;
; |topclock|hour:u3|counter[4]~0          ; |topclock|hour:u3|counter[4]~0          ; combout          ;
; |topclock|hour:u3|LessThan0~57          ; |topclock|hour:u3|LessThan0~57          ; combout          ;
; |topclock|baoshi                        ; |topclock|baoshi                        ; padio            ;
; |topclock|seco[0]                       ; |topclock|seco[0]                       ; padio            ;
; |topclock|seco[1]                       ; |topclock|seco[1]                       ; padio            ;
; |topclock|seco[2]                       ; |topclock|seco[2]                       ; padio            ;
; |topclock|seco[3]                       ; |topclock|seco[3]                       ; padio            ;
; |topclock|seco[4]                       ; |topclock|seco[4]                       ; padio            ;
; |topclock|seco[5]                       ; |topclock|seco[5]                       ; padio            ;
; |topclock|minu[0]                       ; |topclock|minu[0]                       ; padio            ;
; |topclock|minu[1]                       ; |topclock|minu[1]                       ; padio            ;
; |topclock|minu[2]                       ; |topclock|minu[2]                       ; padio            ;
; |topclock|minu[3]                       ; |topclock|minu[3]                       ; padio            ;
; |topclock|minu[4]                       ; |topclock|minu[4]                       ; padio            ;
; |topclock|minu[5]                       ; |topclock|minu[5]                       ; padio            ;
; |topclock|houu[0]                       ; |topclock|houu[0]                       ; padio            ;
; |topclock|houu[1]                       ; |topclock|houu[1]                       ; padio            ;
; |topclock|houu[2]                       ; |topclock|houu[2]                       ; padio            ;
; |topclock|houu[3]                       ; |topclock|houu[3]                       ; padio            ;
; |topclock|reset                         ; |topclock|reset~corein                  ; combout          ;
; |topclock|clk                           ; |topclock|clk~corein                    ; combout          ;
; |topclock|cles                          ; |topclock|cles~corein                   ; combout          ;
; |topclock|clem                          ; |topclock|clem~corein                   ; combout          ;
; |topclock|cleh                          ; |topclock|cleh~corein                   ; combout          ;
; |topclock|clk~clkctrl                   ; |topclock|clk~clkctrl                   ; outclk           ;
; |topclock|minute:u2|carry_out1~clkctrl  ; |topclock|minute:u2|carry_out1~clkctrl  ; outclk           ;
; |topclock|second:u1|carry_out1~clkctrl  ; |topclock|second:u1|carry_out1~clkctrl  ; outclk           ;
; |topclock|minute:u2|counter[5]~0clkctrl ; |topclock|minute:u2|counter[5]~0clkctrl ; outclk           ;
; |topclock|second:u1|counter[5]~0clkctrl ; |topclock|second:u1|counter[5]~0clkctrl ; outclk           ;
; |topclock|hour:u3|counter[4]~0clkctrl   ; |topclock|hour:u3|counter[4]~0clkctrl   ; outclk           ;
+-----------------------------------------+-----------------------------------------+------------------+


The following table displays output ports that do not toggle to 1 during simulation.
+--------------------------------------------------------------------------------------+
; Missing 1-Value Coverage                                                             ;
+---------------------------------+---------------------------------+------------------+
; Node Name                       ; Output Port Name                ; Output Port Type ;
+---------------------------------+---------------------------------+------------------+
; |topclock|hour:u3|counter[4]    ; |topclock|hour:u3|counter[4]    ; regout           ;
; |topclock|hour:u3|counter[3]~72 ; |topclock|hour:u3|counter[3]~73 ; cout             ;
; |topclock|hour:u3|counter[4]~74 ; |topclock|hour:u3|counter[4]~74 ; combout          ;
; |topclock|hour:u3|LessThan0~58  ; |topclock|hour:u3|LessThan0~58  ; combout          ;
; |topclock|alarm                 ; |topclock|alarm                 ; padio            ;
; |topclock|houu[4]               ; |topclock|houu[4]               ; padio            ;
+---------------------------------+---------------------------------+------------------+


The following table displays output ports that do not toggle to 0 during simulation.
+--------------------------------------------------------------------------------------+
; Missing 0-Value Coverage                                                             ;
+---------------------------------+---------------------------------+------------------+
; Node Name                       ; Output Port Name                ; Output Port Type ;
+---------------------------------+---------------------------------+------------------+
; |topclock|hour:u3|counter[4]    ; |topclock|hour:u3|counter[4]    ; regout           ;
; |topclock|hour:u3|counter[3]~72 ; |topclock|hour:u3|counter[3]~73 ; cout             ;
; |topclock|hour:u3|counter[4]~74 ; |topclock|hour:u3|counter[4]~74 ; combout          ;
; |topclock|hour:u3|LessThan0~58  ; |topclock|hour:u3|LessThan0~58  ; combout          ;
; |topclock|alarm                 ; |topclock|alarm                 ; padio            ;
; |topclock|houu[4]               ; |topclock|houu[4]               ; padio            ;
+---------------------------------+---------------------------------+------------------+


+---------------------+
; Simulator INI Usage ;
+--------+------------+
; Option ; Usage      ;
+--------+------------+


+--------------------+
; Simulator Messages ;
+--------------------+
Info: *******************************************************************
Info: Running Quartus II Simulator
    Info: Version 7.2 Build 175 11/20/2007 Service Pack 1 SJ Full Version
    Info: Processing started: Thu Nov 20 00:12:52 2008
Info: Command: quartus_sim --read_settings_files=on --write_settings_files=off topclock -c topclock
Info: Using vector source file "D:/c/haoleba/topclock.vwf"
Info: Option to preserve fewer signal transitions to reduce memory requirements is enabled
    Info: Simulation has been partitioned into sub-simulations according to the maximum transition count determined by the engine. Transitions from memory will be flushed out to disk at the end of each sub-simulation to reduce memory requirements.
Info: Simulation partitioned into 1 sub-simulations
Info: Simulation coverage is      93.48 %
Info: Number of transitions in simulation is 1741277
Info: Quartus II Simulator was successful. 0 errors, 0 warnings
    Info: Allocated 104 megabytes of memory during processing
    Info: Processing ended: Thu Nov 20 00:13:06 2008
    Info: Elapsed time: 00:00:14