topclock.fit.summary

来自「VHDL言语实现的24制时钟,可整点报时,还有闹钟等功能.」· SUMMARY 代码 · 共 17 行

Fitter Status : Successful - Thu Nov 20 00:08:40 2008
Quartus II Version : 7.2 Build 175 11/20/2007 SP 1 SJ Full Version
Revision Name : topclock
Top-level Entity Name : topclock
Family : Cyclone II
Device : EP2C35F672C7
Timing Models : Final
Total logic elements : 28 / 33,216 ( < 1 % )
    Total combinational functions : 28 / 33,216 ( < 1 % )
    Dedicated logic registers : 20 / 33,216 ( < 1 % )
Total registers : 20
Total pins : 36 / 475 ( 8 % )
Total virtual pins : 0
Total memory bits : 0 / 483,840 ( 0 % )
Embedded Multiplier 9-bit elements : 0 / 70 ( 0 % )
Total PLLs : 0 / 4 ( 0 % )