topclock.vhd

VHDL言语实现的24制时钟,可整点报时,还有闹钟等功能.

Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_arith.all;
Use ieee.std_logic_unsigned.all;

Entity topclock is
	Port(clk,reset,enable:in std_logic;  
		cles,clem,cleh:in std_logic;
		setm: in std_logic_vector(5 downto 0);
        seth: in std_logic_vector(4 downto 0);
		alarm,baoshi:out std_logic;
		seco,minu:  out std_logic_vector(5 downto 0);
		houu : out std_logic_vector(4 downto 0));
		
End topclock;

Architecture one of topclock is

Component second                                   
	 port(reset,clk,cles: in std_logic; 
       spe:out std_logic;
     sec : out std_logic_vector(5 downto 0); 
     enmin : out std_logic);   	  
End Component;

Component minute                                      
	port(reset,clkm,clem : in std_logic; 
     min : out std_logic_vector(5 downto 0); 
     enhou,speak : out std_logic); 
End Component;

Component hour                                       
	port(reset,clkh,cleh: in std_logic; 
     hou : out std_logic_vector(4 downto 0)); 
End Component;
 
component alar
   Port(enable,reset:in std_logic;
       setm:in std_logic_vector(5 downto 0);
       seth: in std_logic_vector(4 downto 0);                
       minu1:in std_logic_vector(5 downto 0);
       houu1:in std_logic_vector(4 downto 0);
       alarm:out std_logic);  
end component;
signal sthmi,steho:std_logic;
signal enm,enh:std_logic;                
signal a,b:std_logic;
signal m:std_logic_vector(5 downto 0);
signal h:std_logic_vector(4 downto 0);
begin
	u1:second port map(reset=>reset,clk=>clk,cles=>cles,sec=>seco,spe=>a,enmin=>enm);
	u2:minute port map(reset=>reset,clem=>clem,min=>m,speak=>b,clkm=>enm,enhou=>enh);
	u3:hour port map(reset=>reset,cleh=>cleh,hou=>h,clkh=>enh);
	u4:alar port map(reset=>reset,enable=>enable,setm=>setm,seth=>seth,alarm=>alarm,minu1=>m,houu1=>h);
	minu<=m;
	houu<=h;
	baoshi<=(a and b);
end;


library ieee; 
use ieee.std_logic_1164.all; 
use ieee.std_logic_unsigned.all; 
entity second is 
port(reset,clk,setmin,cles: in std_logic;
     spe : out std_logic; 
     sec : out std_logic_vector(5 downto 0); 
     enmin : out std_logic); 
end second; 
architecture behav of second is 
signal counter : std_logic_vector(5 downto 0); 
signal carry_out1 : std_logic;
signal carry_out2 : std_logic;  
begin 
 process(reset,clk) 
begin 
if reset='0' then  
   counter<="000000"; 
   
elsif(clk'event and clk='1') then 
 
   if (counter<59) then 
       counter<=counter + 1; 
       carry_out1<='0';
       else 
         counter<="000000";
         carry_out1<='1';
    end if;
   if (counter<3) then
     carry_out2<='1';
    else carry_out2<='0';
   end if; 
end if; 
if cles='0' then
     counter<="000000";
 end if;
end process; 
sec<=counter; 
enmin<=carry_out1; 
spe<=carry_out2;
end behav; 

library ieee; 
use ieee.std_logic_1164.all; 
use ieee.std_logic_unsigned.all; 
entity minute is 
port(reset,clkm,clem : in std_logic; 
     min : out std_logic_vector(5 downto 0); 
     enhou,speak : out std_logic); 
end minute; 
architecture behav of minute is 
signal counter : std_logic_vector(5 downto 0); 
signal carry_out1 : std_logic;  
begin 
 process(reset,clkm) 
begin 
if reset='0' then  
   counter<="000000"; 
elsif(clkm'event and clkm='1') then 
   if (counter<59) then 
       counter<=counter + 1; 
       carry_out1<='0';
       else 
         counter<="000000";
         carry_out1<='1'; 
    end if;  
end if; 
if clem='0' then
  counter<="000000";
end if;
end process; 
min<=counter; 
enhou<=carry_out1; 
speak<=carry_out1;
end behav; 



library ieee; 
use ieee.std_logic_1164.all; 
use ieee.std_logic_unsigned.all; 
entity hour is 
port(reset,clkh,cleh: in std_logic; 
     hou : out std_logic_vector(4 downto 0)); 
end hour; 
architecture behav of hour is 
signal counter : std_logic_vector(4 downto 0); 
begin 
 process(reset,clkh) 
begin 

if reset='0' then
   counter<="00000"; 
elsif(clkh'event and clkh='1') then 
   if (counter<23) then 
          counter<=counter + 1; 
       else 
         counter<="00000";
    end if;
 end if;
 if cleh='0' then
   counter<="00000";
end if;
end process; 
hou<=counter; 
end behav;

Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_arith.all;
Use ieee.std_logic_unsigned.all;
Entity alar is
  Port(enable,reset:in std_logic;
       setm:in std_logic_vector(5 downto 0);
       seth: in std_logic_vector(4 downto 0);                
       minu1:in std_logic_vector(5 downto 0);
       houu1:in std_logic_vector(4 downto 0);
       alarm:out std_logic);  
End alar;
Architecture a of alar is
 signal al:std_logic;
 Begin
   process(enable,reset)
 begin
   if reset='0' then
      al<='0';
      elsif (setm=minu1 and seth=houu1) then
       al<='1';
      else al<='0';
   end if;
 if enable='1' then
   al<='0';
   else al<=al;
 end if;
   end process;
  alarm<=al;
end a;