📄 prev_cmp_fpga_uartrw.qmsg
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{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Info: Assembler is generating device programming files" { } { } 0 0 "Assembler is generating device programming files" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II " "Info: Quartus II Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "139 " "Info: Allocated 139 megabytes of memory during processing" { } { } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Wed May 07 10:01:02 2008 " "Info: Processing ended: Wed May 07 10:01:02 2008" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:08 " "Info: Elapsed time: 00:00:08" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.1 Build 156 04/30/2007 SJ Full Version " "Info: Version 7.1 Build 156 04/30/2007 SJ Full Version" { } { } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed May 07 10:01:03 2008 " "Info: Processing started: Wed May 07 10:01:03 2008" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off fpga_uartrw -c fpga_uartrw --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off fpga_uartrw -c fpga_uartrw --timing_analysis_only" { } { } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" { } { { "fpga_uartrw.bdf" "" { Schematic "D:/altera/71/jiangbinbin/fpga_uartrw/fpga_uartrw.bdf" { { 136 -48 120 152 "clk" "" } } } } { "d:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } } } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0} } { } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register uart_receiver:inst1\|bit_spacing\[0\] register uart_receiver:inst1\|RxD_data\[6\] 234.91 MHz 4.257 ns Internal " "Info: Clock \"clk\" has Internal fmax of 234.91 MHz between source register \"uart_receiver:inst1\|bit_spacing\[0\]\" and destination register \"uart_receiver:inst1\|RxD_data\[6\]\" (period= 4.257 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.018 ns + Longest register register " "Info: + Longest register to register delay is 4.018 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns uart_receiver:inst1\|bit_spacing\[0\] 1 REG LCFF_X16_Y9_N27 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X16_Y9_N27; Fanout = 5; REG Node = 'uart_receiver:inst1\|bit_spacing\[0\]'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { uart_receiver:inst1|bit_spacing[0] } "NODE_NAME" } } { "fpga_receiver.v" "" { Text "D:/altera/71/jiangbinbin/fpga_uartrw/fpga_receiver.v" 63 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.738 ns) + CELL(0.544 ns) 1.282 ns uart_receiver:inst1\|Equal2~43 2 COMB LCCOMB_X17_Y9_N24 7 " "Info: 2: + IC(0.738 ns) + CELL(0.544 ns) = 1.282 ns; Loc. = LCCOMB_X17_Y9_N24; Fanout = 7; COMB Node = 'uart_receiver:inst1\|Equal2~43'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.282 ns" { uart_receiver:inst1|bit_spacing[0] uart_receiver:inst1|Equal2~43 } "NODE_NAME" } } { "fpga_receiver.v" "" { Text "D:/altera/71/jiangbinbin/fpga_uartrw/fpga_receiver.v" 61 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.423 ns) + CELL(0.370 ns) 2.075 ns uart_receiver:inst1\|always5~12 3 COMB LCCOMB_X17_Y9_N6 8 " "Info: 3: + IC(0.423 ns) + CELL(0.370 ns) = 2.075 ns; Loc. = LCCOMB_X17_Y9_N6; Fanout = 8; COMB Node = 'uart_receiver:inst1\|always5~12'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.793 ns" { uart_receiver:inst1|Equal2~43 uart_receiver:inst1|always5~12 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.088 ns) + CELL(0.855 ns) 4.018 ns uart_receiver:inst1\|RxD_data\[6\] 4 REG LCFF_X17_Y13_N11 2 " "Info: 4: + IC(1.088 ns) + CELL(0.855 ns) = 4.018 ns; Loc. = LCFF_X17_Y13_N11; Fanout = 2; REG Node = 'uart_receiver:inst1\|RxD_data\[6\]'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.943 ns" { uart_receiver:inst1|always5~12 uart_receiver:inst1|RxD_data[6] } "NODE_NAME" } } { "fpga_receiver.v" "" { Text "D:/altera/71/jiangbinbin/fpga_uartrw/fpga_receiver.v" 128 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.769 ns ( 44.03 % ) " "Info: Total cell delay = 1.769 ns ( 44.03 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.249 ns ( 55.97 % ) " "Info: Total interconnect delay = 2.249 ns ( 55.97 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.018 ns" { uart_receiver:inst1|bit_spacing[0] uart_receiver:inst1|Equal2~43 uart_receiver:inst1|always5~12 uart_receiver:inst1|RxD_data[6] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "4.018 ns" { uart_receiver:inst1|bit_spacing[0] uart_receiver:inst1|Equal2~43 uart_receiver:inst1|always5~12 uart_receiver:inst1|RxD_data[6] } { 0.000ns 0.738ns 0.423ns 1.088ns } { 0.000ns 0.544ns 0.370ns 0.855ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.025 ns - Smallest " "Info: - Smallest clock skew is 0.025 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.859 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.859 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'clk'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "fpga_uartrw.bdf" "" { Schematic "D:/altera/71/jiangbinbin/fpga_uartrw/fpga_uartrw.bdf" { { 136 -48 120 152 "clk" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.279 ns clk~clkctrl 2 COMB CLKCTRL_G2 66 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.279 ns; Loc. = CLKCTRL_G2; Fanout = 66; COMB Node = 'clk~clkctrl'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { clk clk~clkctrl } "NODE_NAME" } } { "fpga_uartrw.bdf" "" { Schematic "D:/altera/71/jiangbinbin/fpga_uartrw/fpga_uartrw.bdf" { { 136 -48 120 152 "clk" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.914 ns) + CELL(0.666 ns) 2.859 ns uart_receiver:inst1\|RxD_data\[6\] 3 REG LCFF_X17_Y13_N11 2 " "Info: 3: + IC(0.914 ns) + CELL(0.666 ns) = 2.859 ns; Loc. = LCFF_X17_Y13_N11; Fanout = 2; REG Node = 'uart_receiver:inst1\|RxD_data\[6\]'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.580 ns" { clk~clkctrl uart_receiver:inst1|RxD_data[6] } "NODE_NAME" } } { "fpga_receiver.v" "" { Text "D:/altera/71/jiangbinbin/fpga_uartrw/fpga_receiver.v" 128 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 63.17 % ) " "Info: Total cell delay = 1.806 ns ( 63.17 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.053 ns ( 36.83 % ) " "Info: Total interconnect delay = 1.053 ns ( 36.83 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.859 ns" { clk clk~clkctrl uart_receiver:inst1|RxD_data[6] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.859 ns" { clk clk~combout clk~clkctrl uart_receiver:inst1|RxD_data[6] } { 0.000ns 0.000ns 0.139ns 0.914ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.834 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.834 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'clk'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "fpga_uartrw.bdf" "" { Schematic "D:/altera/71/jiangbinbin/fpga_uartrw/fpga_uartrw.bdf" { { 136 -48 120 152 "clk" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.279 ns clk~clkctrl 2 COMB CLKCTRL_G2 66 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.279 ns; Loc. = CLKCTRL_G2; Fanout = 66; COMB Node = 'clk~clkctrl'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { clk clk~clkctrl } "NODE_NAME" } } { "fpga_uartrw.bdf" "" { Schematic "D:/altera/71/jiangbinbin/fpga_uartrw/fpga_uartrw.bdf" { { 136 -48 120 152 "clk" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.889 ns) + CELL(0.666 ns) 2.834 ns uart_receiver:inst1\|bit_spacing\[0\] 3 REG LCFF_X16_Y9_N27 5 " "Info: 3: + IC(0.889 ns) + CELL(0.666 ns) = 2.834 ns; Loc. = LCFF_X16_Y9_N27; Fanout = 5; REG Node = 'uart_receiver:inst1\|bit_spacing\[0\]'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.555 ns" { clk~clkctrl uart_receiver:inst1|bit_spacing[0] } "NODE_NAME" } } { "fpga_receiver.v" "" { Text "D:/altera/71/jiangbinbin/fpga_uartrw/fpga_receiver.v" 63 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 63.73 % ) " "Info: Total cell delay = 1.806 ns ( 63.73 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.028 ns ( 36.27 % ) " "Info: Total interconnect delay = 1.028 ns ( 36.27 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.834 ns" { clk clk~clkctrl uart_receiver:inst1|bit_spacing[0] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.834 ns" { clk clk~combout clk~clkctrl uart_receiver:inst1|bit_spacing[0] } { 0.000ns 0.000ns 0.139ns 0.889ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.859 ns" { clk clk~clkctrl uart_receiver:inst1|RxD_data[6] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.859 ns" { clk clk~combout clk~clkctrl uart_receiver:inst1|RxD_data[6] } { 0.000ns 0.000ns 0.139ns 0.914ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.834 ns" { clk clk~clkctrl uart_receiver:inst1|bit_spacing[0] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.834 ns" { clk clk~combout clk~clkctrl uart_receiver:inst1|bit_spacing[0] } { 0.000ns 0.000ns 0.139ns 0.889ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" { } { { "fpga_receiver.v" "" { Text "D:/altera/71/jiangbinbin/fpga_uartrw/fpga_receiver.v" 63 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" { } { { "fpga_receiver.v" "" { Text "D:/altera/71/jiangbinbin/fpga_uartrw/fpga_receiver.v" 128 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.018 ns" { uart_receiver:inst1|bit_spacing[0] uart_receiver:inst1|Equal2~43 uart_receiver:inst1|always5~12 uart_receiver:inst1|RxD_data[6] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "4.018 ns" { uart_receiver:inst1|bit_spacing[0] uart_receiver:inst1|Equal2~43 uart_receiver:inst1|always5~12 uart_receiver:inst1|RxD_data[6] } { 0.000ns 0.738ns 0.423ns 1.088ns } { 0.000ns 0.544ns 0.370ns 0.855ns } "" } } { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.859 ns" { clk clk~clkctrl uart_receiver:inst1|RxD_data[6] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.859 ns" { clk clk~combout clk~clkctrl uart_receiver:inst1|RxD_data[6] } { 0.000ns 0.000ns 0.139ns 0.914ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.834 ns" { clk clk~clkctrl uart_receiver:inst1|bit_spacing[0] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.834 ns" { clk clk~combout clk~clkctrl uart_receiver:inst1|bit_spacing[0] } { 0.000ns 0.000ns 0.139ns 0.889ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Info" "ITDB_TSU_RESULT" "uart_receiver:inst1\|RxD_sync_inv\[0\] uart_rxd clk 5.284 ns register " "Info: tsu for register \"uart_receiver:inst1\|RxD_sync_inv\[0\]\" (data pin = \"uart_rxd\", clock pin = \"clk\") is 5.284 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.158 ns + Longest pin register " "Info: + Longest pin to register delay is 8.158 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.015 ns) 1.015 ns uart_rxd 1 PIN PIN_106 1 " "Info: 1: + IC(0.000 ns) + CELL(1.015 ns) = 1.015 ns; Loc. = PIN_106; Fanout = 1; PIN Node = 'uart_rxd'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { uart_rxd } "NODE_NAME" } } { "fpga_uartrw.bdf" "" { Schematic "D:/altera/71/jiangbinbin/fpga_uartrw/fpga_uartrw.bdf" { { 168 -48 120 184 "uart_rxd" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(6.833 ns) + CELL(0.202 ns) 8.050 ns uart_receiver:inst1\|RxD_sync_inv\[0\]~173 2 COMB LCCOMB_X16_Y9_N6 1 " "Info: 2: + IC(6.833 ns) + CELL(0.202 ns) = 8.050 ns; Loc. = LCCOMB_X16_Y9_N6; Fanout = 1; COMB Node = 'uart_receiver:inst1\|RxD_sync_inv\[0\]~173'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.035 ns" { uart_rxd uart_receiver:inst1|RxD_sync_inv[0]~173 } "NODE_NAME" } } { "fpga_receiver.v" "" { Text "D:/altera/71/jiangbinbin/fpga_uartrw/fpga_receiver.v" 31 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 8.158 ns uart_receiver:inst1\|RxD_sync_inv\[0\] 3 REG LCFF_X16_Y9_N7 1 " "Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 8.158 ns; Loc. = LCFF_X16_Y9_N7; Fanout = 1; REG Node = 'uart_receiver:inst1\|RxD_sync_inv\[0\]'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { uart_receiver:inst1|RxD_sync_inv[0]~173 uart_receiver:inst1|RxD_sync_inv[0] } "NODE_NAME" } } { "fpga_receiver.v" "" { Text "D:/altera/71/jiangbinbin/fpga_uartrw/fpga_receiver.v" 31 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.325 ns ( 16.24 % ) " "Info: Total cell delay = 1.325 ns ( 16.24 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.833 ns ( 83.76 % ) " "Info: Total interconnect delay = 6.833 ns ( 83.76 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "8.158 ns" { uart_rxd uart_receiver:inst1|RxD_sync_inv[0]~173 uart_receiver:inst1|RxD_sync_inv[0] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "8.158 ns" { uart_rxd uart_rxd~combout uart_receiver:inst1|RxD_sync_inv[0]~173 uart_receiver:inst1|RxD_sync_inv[0] } { 0.000ns 0.000ns 6.833ns 0.000ns } { 0.000ns 1.015ns 0.202ns 0.108ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" { } { { "fpga_receiver.v" "" { Text "D:/altera/71/jiangbinbin/fpga_uartrw/fpga_receiver.v" 31 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.834 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.834 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'clk'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "fpga_uartrw.bdf" "" { Schematic "D:/altera/71/jiangbinbin/fpga_uartrw/fpga_uartrw.bdf" { { 136 -48 120 152 "clk" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.279 ns clk~clkctrl 2 COMB CLKCTRL_G2 66 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.279 ns; Loc. = CLKCTRL_G2; Fanout = 66; COMB Node = 'clk~clkctrl'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { clk clk~clkctrl } "NODE_NAME" } } { "fpga_uartrw.bdf" "" { Schematic "D:/altera/71/jiangbinbin/fpga_uartrw/fpga_uartrw.bdf" { { 136 -48 120 152 "clk" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.889 ns) + CELL(0.666 ns) 2.834 ns uart_receiver:inst1\|RxD_sync_inv\[0\] 3 REG LCFF_X16_Y9_N7 1 " "Info: 3: + IC(0.889 ns) + CELL(0.666 ns) = 2.834 ns; Loc. = LCFF_X16_Y9_N7; Fanout = 1; REG Node = 'uart_receiver:inst1\|RxD_sync_inv\[0\]'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.555 ns" { clk~clkctrl uart_receiver:inst1|RxD_sync_inv[0] } "NODE_NAME" } } { "fpga_receiver.v" "" { Text "D:/altera/71/jiangbinbin/fpga_uartrw/fpga_receiver.v" 31 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 63.73 % ) " "Info: Total cell delay = 1.806 ns ( 63.73 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.028 ns ( 36.27 % ) " "Info: Total interconnect delay = 1.028 ns ( 36.27 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.834 ns" { clk clk~clkctrl uart_receiver:inst1|RxD_sync_inv[0] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.834 ns" { clk clk~combout clk~clkctrl uart_receiver:inst1|RxD_sync_inv[0] } { 0.000ns 0.000ns 0.139ns 0.889ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "8.158 ns" { uart_rxd uart_receiver:inst1|RxD_sync_inv[0]~173 uart_receiver:inst1|RxD_sync_inv[0] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "8.158 ns" { uart_rxd uart_rxd~combout uart_receiver:inst1|RxD_sync_inv[0]~173 uart_receiver:inst1|RxD_sync_inv[0] } { 0.000ns 0.000ns 6.833ns 0.000ns } { 0.000ns 1.015ns 0.202ns 0.108ns } "" } } { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.834 ns" { clk clk~clkctrl uart_receiver:inst1|RxD_sync_inv[0] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.834 ns" { clk clk~combout clk~clkctrl uart_receiver:inst1|RxD_sync_inv[0] } { 0.000ns 0.000ns 0.139ns 0.889ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk txd_busy_led uart_transmitter:inst\|state\[1\] 10.465 ns register " "Info: tco from clock \"clk\" to destination pin \"txd_busy_led\" through register \"uart_transmitter:inst\|state\[1\]\" is 10.465 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.872 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.872 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'clk'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "fpga_uartrw.bdf" "" { Schematic "D:/altera/71/jiangbinbin/fpga_uartrw/fpga_uartrw.bdf" { { 136 -48 120 152 "clk" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.279 ns clk~clkctrl 2 COMB CLKCTRL_G2 66 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.279 ns; Loc. = CLKCTRL_G2; Fanout = 66; COMB Node = 'clk~clkctrl'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { clk clk~clkctrl } "NODE_NAME" } } { "fpga_uartrw.bdf" "" { Schematic "D:/altera/71/jiangbinbin/fpga_uartrw/fpga_uartrw.bdf" { { 136 -48 120 152 "clk" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.927 ns) + CELL(0.666 ns) 2.872 ns uart_transmitter:inst\|state\[1\] 3 REG LCFF_X17_Y14_N21 11 " "Info: 3: + IC(0.927 ns) + CELL(0.666 ns) = 2.872 ns; Loc. = LCFF_X17_Y14_N21; Fanout = 11; REG Node = 'uart_transmitter:inst\|state\[1\]'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.593 ns" { clk~clkctrl uart_transmitter:inst|state[1] } "NODE_NAME" } } { "fpga_transmitter.v" "" { Text "D:/altera/71/jiangbinbin/fpga_uartrw/fpga_transmitter.v" 49 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 62.88 % ) " "Info: Total cell delay = 1.806 ns ( 62.88 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.066 ns ( 37.12 % ) " "Info: Total interconnect delay = 1.066 ns ( 37.12 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.872 ns" { clk clk~clkctrl uart_transmitter:inst|state[1] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.872 ns" { clk clk~combout clk~clkctrl uart_transmitter:inst|state[1] } { 0.000ns 0.000ns 0.139ns 0.927ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" { } { { "fpga_transmitter.v" "" { Text "D:/altera/71/jiangbinbin/fpga_uartrw/fpga_transmitter.v" 49 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.289 ns + Longest register pin " "Info: + Longest register to pin delay is 7.289 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns uart_transmitter:inst\|state\[1\] 1 REG LCFF_X17_Y14_N21 11 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X17_Y14_N21; Fanout = 11; REG Node = 'uart_transmitter:inst\|state\[1\]'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { uart_transmitter:inst|state[1] } "NODE_NAME" } } { "fpga_transmitter.v" "" { Text "D:/altera/71/jiangbinbin/fpga_uartrw/fpga_transmitter.v" 49 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.143 ns) + CELL(0.534 ns) 1.677 ns uart_transmitter:inst\|Equal0~87 2 COMB LCCOMB_X16_Y14_N28 18 " "Info: 2: + IC(1.143 ns) + CELL(0.534 ns) = 1.677 ns; Loc. = LCCOMB_X16_Y14_N28; Fanout = 18; COMB Node = 'uart_transmitter:inst\|Equal0~87'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.677 ns" { uart_transmitter:inst|state[1] uart_transmitter:inst|Equal0~87 } "NODE_NAME" } } { "fpga_transmitter.v" "" { Text "D:/altera/71/jiangbinbin/fpga_uartrw/fpga_transmitter.v" 37 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.496 ns) + CELL(3.116 ns) 7.289 ns txd_busy_led 3 PIN PIN_5 0 " "Info: 3: + IC(2.496 ns) + CELL(3.116 ns) = 7.289 ns; Loc. = PIN_5; Fanout = 0; PIN Node = 'txd_busy_led'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "5.612 ns" { uart_transmitter:inst|Equal0~87 txd_busy_led } "NODE_NAME" } } { "fpga_uartrw.bdf" "" { Schematic "D:/altera/71/jiangbinbin/fpga_uartrw/fpga_uartrw.bdf" { { 168 584 760 184 "txd_busy_led" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.650 ns ( 50.08 % ) " "Info: Total cell delay = 3.650 ns ( 50.08 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.639 ns ( 49.92 % ) " "Info: Total interconnect delay = 3.639 ns ( 49.92 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.289 ns" { uart_transmitter:inst|state[1] uart_transmitter:inst|Equal0~87 txd_busy_led } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.289 ns" { uart_transmitter:inst|state[1] uart_transmitter:inst|Equal0~87 txd_busy_led } { 0.000ns 1.143ns 2.496ns } { 0.000ns 0.534ns 3.116ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.872 ns" { clk clk~clkctrl uart_transmitter:inst|state[1] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.872 ns" { clk clk~combout clk~clkctrl uart_transmitter:inst|state[1] } { 0.000ns 0.000ns 0.139ns 0.927ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.289 ns" { uart_transmitter:inst|state[1] uart_transmitter:inst|Equal0~87 txd_busy_led } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.289 ns" { uart_transmitter:inst|state[1] uart_transmitter:inst|Equal0~87 txd_busy_led } { 0.000ns 1.143ns 2.496ns } { 0.000ns 0.534ns 3.116ns } "" } } } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_TH_RESULT" "uart_receiver:inst1\|RxD_sync_inv\[0\] uart_rxd clk -5.018 ns register " "Info: th for register \"uart_receiver:inst1\|RxD_sync_inv\[0\]\" (data pin = \"uart_rxd\", clock pin = \"clk\") is -5.018 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.834 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 2.834 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'clk'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "fpga_uartrw.bdf" "" { Schematic "D:/altera/71/jiangbinbin/fpga_uartrw/fpga_uartrw.bdf" { { 136 -48 120 152 "clk" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.279 ns clk~clkctrl 2 COMB CLKCTRL_G2 66 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.279 ns; Loc. = CLKCTRL_G2; Fanout = 66; COMB Node = 'clk~clkctrl'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { clk clk~clkctrl } "NODE_NAME" } } { "fpga_uartrw.bdf" "" { Schematic "D:/altera/71/jiangbinbin/fpga_uartrw/fpga_uartrw.bdf" { { 136 -48 120 152 "clk" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.889 ns) + CELL(0.666 ns) 2.834 ns uart_receiver:inst1\|RxD_sync_inv\[0\] 3 REG LCFF_X16_Y9_N7 1 " "Info: 3: + IC(0.889 ns) + CELL(0.666 ns) = 2.834 ns; Loc. = LCFF_X16_Y9_N7; Fanout = 1; REG Node = 'uart_receiver:inst1\|RxD_sync_inv\[0\]'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.555 ns" { clk~clkctrl uart_receiver:inst1|RxD_sync_inv[0] } "NODE_NAME" } } { "fpga_receiver.v" "" { Text "D:/altera/71/jiangbinbin/fpga_uartrw/fpga_receiver.v" 31 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 63.73 % ) " "Info: Total cell delay = 1.806 ns ( 63.73 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.028 ns ( 36.27 % ) " "Info: Total interconnect delay = 1.028 ns ( 36.27 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.834 ns" { clk clk~clkctrl uart_receiver:inst1|RxD_sync_inv[0] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.834 ns" { clk clk~combout clk~clkctrl uart_receiver:inst1|RxD_sync_inv[0] } { 0.000ns 0.000ns 0.139ns 0.889ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.306 ns + " "Info: + Micro hold delay of destination is 0.306 ns" { } { { "fpga_receiver.v" "" { Text "D:/altera/71/jiangbinbin/fpga_uartrw/fpga_receiver.v" 31 -1 0 } } } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.158 ns - Shortest pin register " "Info: - Shortest pin to register delay is 8.158 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.015 ns) 1.015 ns uart_rxd 1 PIN PIN_106 1 " "Info: 1: + IC(0.000 ns) + CELL(1.015 ns) = 1.015 ns; Loc. = PIN_106; Fanout = 1; PIN Node = 'uart_rxd'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { uart_rxd } "NODE_NAME" } } { "fpga_uartrw.bdf" "" { Schematic "D:/altera/71/jiangbinbin/fpga_uartrw/fpga_uartrw.bdf" { { 168 -48 120 184 "uart_rxd" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(6.833 ns) + CELL(0.202 ns) 8.050 ns uart_receiver:inst1\|RxD_sync_inv\[0\]~173 2 COMB LCCOMB_X16_Y9_N6 1 " "Info: 2: + IC(6.833 ns) + CELL(0.202 ns) = 8.050 ns; Loc. = LCCOMB_X16_Y9_N6; Fanout = 1; COMB Node = 'uart_receiver:inst1\|RxD_sync_inv\[0\]~173'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.035 ns" { uart_rxd uart_receiver:inst1|RxD_sync_inv[0]~173 } "NODE_NAME" } } { "fpga_receiver.v" "" { Text "D:/altera/71/jiangbinbin/fpga_uartrw/fpga_receiver.v" 31 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 8.158 ns uart_receiver:inst1\|RxD_sync_inv\[0\] 3 REG LCFF_X16_Y9_N7 1 " "Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 8.158 ns; Loc. = LCFF_X16_Y9_N7; Fanout = 1; REG Node = 'uart_receiver:inst1\|RxD_sync_inv\[0\]'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { uart_receiver:inst1|RxD_sync_inv[0]~173 uart_receiver:inst1|RxD_sync_inv[0] } "NODE_NAME" } } { "fpga_receiver.v" "" { Text "D:/altera/71/jiangbinbin/fpga_uartrw/fpga_receiver.v" 31 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.325 ns ( 16.24 % ) " "Info: Total cell delay = 1.325 ns ( 16.24 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.833 ns ( 83.76 % ) " "Info: Total interconnect delay = 6.833 ns ( 83.76 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "8.158 ns" { uart_rxd uart_receiver:inst1|RxD_sync_inv[0]~173 uart_receiver:inst1|RxD_sync_inv[0] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "8.158 ns" { uart_rxd uart_rxd~combout uart_receiver:inst1|RxD_sync_inv[0]~173 uart_receiver:inst1|RxD_sync_inv[0] } { 0.000ns 0.000ns 6.833ns 0.000ns } { 0.000ns 1.015ns 0.202ns 0.108ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.834 ns" { clk clk~clkctrl uart_receiver:inst1|RxD_sync_inv[0] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.834 ns" { clk clk~combout clk~clkctrl uart_receiver:inst1|RxD_sync_inv[0] } { 0.000ns 0.000ns 0.139ns 0.889ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "8.158 ns" { uart_rxd uart_receiver:inst1|RxD_sync_inv[0]~173 uart_receiver:inst1|RxD_sync_inv[0] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "8.158 ns" { uart_rxd uart_rxd~combout uart_receiver:inst1|RxD_sync_inv[0]~173 uart_receiver:inst1|RxD_sync_inv[0] } { 0.000ns 0.000ns 6.833ns 0.000ns } { 0.000ns 1.015ns 0.202ns 0.108ns } "" } } } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 1 Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "110 " "Info: Allocated 110 megabytes of memory during processing" { } { } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Wed May 07 10:01:03 2008 " "Info: Processing ended: Wed May 07 10:01:03 2008" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0⌨️ 快捷键说明
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