fpga_uartrw.fit.rpt

FPGA的uart控制器的verilog源程序

; Ignore PLL Mode When Merging PLLs                                     ; Off                            ; Off                            ;
; Perform Physical Synthesis for Combinational Logic for Fitting        ; Off                            ; Off                            ;
; Perform Physical Synthesis for Combinational Logic for Performance    ; Off                            ; Off                            ;
; Perform Register Duplication for Performance                          ; Off                            ; Off                            ;
; Perform Logic to Memory Mapping for Fitting                           ; Off                            ; Off                            ;
; Perform Register Retiming for Performance                             ; Off                            ; Off                            ;
; Perform Asynchronous Signal Pipelining                                ; Off                            ; Off                            ;
; Fitter Effort                                                         ; Auto Fit                       ; Auto Fit                       ;
; Physical Synthesis Effort Level                                       ; Normal                         ; Normal                         ;
; Auto Global Clock                                                     ; On                             ; On                             ;
; Auto Global Register Control Signals                                  ; On                             ; On                             ;
; Stop After Congestion Map Generation                                  ; Off                            ; Off                            ;
; Save Intermediate Fitting Results                                     ; Off                            ; Off                            ;
; Use smart compilation                                                 ; Off                            ; Off                            ;
+-----------------------------------------------------------------------+--------------------------------+--------------------------------+


+--------------+
; Pin-Out File ;
+--------------+
The pin-out file can be found in D:/altera/71/jiangbinbin/fpga_uartrw/fpga_uartrw.pin.


+-------------------------------------------------------------------------------+
; Fitter Resource Usage Summary                                                 ;
+---------------------------------------------+---------------------------------+
; Resource                                    ; Usage                           ;
+---------------------------------------------+---------------------------------+
; Total logic elements                        ; 87 / 8,256 ( 1 % )              ;
;     -- Combinational with no register       ; 21                              ;
;     -- Register only                        ; 12                              ;
;     -- Combinational with a register        ; 54                              ;
;                                             ;                                 ;
; Logic element usage by number of LUT inputs ;                                 ;
;     -- 4 input functions                    ; 27                              ;
;     -- 3 input functions                    ; 9                               ;
;     -- <=2 input functions                  ; 39                              ;
;     -- Register only                        ; 12                              ;
;                                             ;                                 ;
; Logic elements by mode                      ;                                 ;
;     -- normal mode                          ; 46                              ;
;     -- arithmetic mode                      ; 29                              ;
;                                             ;                                 ;
; Total registers*                            ; 66 / 8,646 ( < 1 % )            ;
;     -- Dedicated logic registers            ; 66 / 8,256 ( < 1 % )            ;
;     -- I/O registers                        ; 0 / 390 ( 0 % )                 ;
;                                             ;                                 ;
; Total LABs:  partially or completely used   ; 8 / 516 ( 2 % )                 ;
; User inserted logic elements                ; 0                               ;
; Virtual pins                                ; 0                               ;
; I/O pins                                    ; 5 / 138 ( 4 % )                 ;
;     -- Clock pins                           ; 1 / 4 ( 25 % )                  ;
; Global signals                              ; 1                               ;
; M4Ks                                        ; 0 / 36 ( 0 % )                  ;
; Total memory bits                           ; 0 / 165,888 ( 0 % )             ;
; Total RAM block bits                        ; 0 / 165,888 ( 0 % )             ;
; Embedded Multiplier 9-bit elements          ; 0 / 36 ( 0 % )                  ;
; PLLs                                        ; 0 / 2 ( 0 % )                   ;
; Global clocks                               ; 1 / 8 ( 13 % )                  ;
; Average interconnect usage                  ; 0%                              ;
; Peak interconnect usage                     ; 0%                              ;
; Maximum fan-out node                        ; clk~clkctrl                     ;
; Maximum fan-out                             ; 66                              ;
; Highest non-global fan-out signal           ; uart_transmitter:inst|Equal0~87 ;
; Highest non-global fan-out                  ; 18                              ;
; Total fan-out                               ; 394                             ;
; Average fan-out                             ; 2.49                            ;
+---------------------------------------------+---------------------------------+
*  Register count does not include registers inside RAM blocks or DSP blocks.



+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Input Pins                                                                                                                                                                                                                                                     ;
+----------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
; Name     ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Location assigned by ;
+----------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
; clk      ; 23    ; 1        ; 0            ; 9            ; 0           ; 1                     ; 0                  ; yes    ; no             ; no            ; no              ; no       ; Off          ; 3.3-V LVTTL  ; Off         ; User                 ;
; uart_rxd ; 106   ; 3        ; 34           ; 1            ; 1           ; 1                     ; 0                  ; no     ; no             ; no            ; no              ; no       ; Off          ; 3.3-V LVTTL  ; Off         ; User                 ;
+----------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Output Pins                                                                                                                                                                                                                                                                                    ;
+---------------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+------+
; Name          ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Output Register ; Output Enable Register ; Power Up High ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Location assigned by ; Load ;
+---------------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+------+
; rxd_ready_led ; 4     ; 1        ; 0            ; 18           ; 3           ; no              ; no                     ; no            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 24mA             ; Off         ; User                 ; 0 pF ;
; txd_busy_led  ; 5     ; 1        ; 0            ; 17           ; 0           ; no              ; no                     ; no            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 24mA             ; Off         ; User                 ; 0 pF ;
; uart_txd      ; 107   ; 3        ; 34           ; 2            ; 1           ; no              ; no                     ; no            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 24mA             ; Off         ; User                 ; 0 pF ;
+---------------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+------+


+-----------------------------------------------------------+
; I/O Bank Usage                                            ;
+----------+-----------------+---------------+--------------+
; I/O Bank ; Usage           ; VCCIO Voltage ; VREF Voltage ;
+----------+-----------------+---------------+--------------+
; 1        ; 5 / 32 ( 16 % ) ; 3.3V          ; --           ;
; 2        ; 0 / 35 ( 0 % )  ; 3.3V          ; --           ;
; 3        ; 3 / 35 ( 9 % )  ; 3.3V          ; --           ;
; 4        ; 0 / 36 ( 0 % )  ; 3.3V          ; --           ;
+----------+-----------------+---------------+--------------+