fpga_uartrw.map.rpt

FPGA的uart控制器的verilog源程序

+---------------------------------------------+-------+
; Estimated Total logic elements              ; 75    ;
;                                             ;       ;
; Total combinational functions               ; 75    ;
; Logic element usage by number of LUT inputs ;       ;
;     -- 4 input functions                    ; 27    ;
;     -- 3 input functions                    ; 9     ;
;     -- <=2 input functions                  ; 39    ;
;                                             ;       ;
; Logic elements by mode                      ;       ;
;     -- normal mode                          ; 46    ;
;     -- arithmetic mode                      ; 29    ;
;                                             ;       ;
; Total registers                             ; 66    ;
;     -- Dedicated logic registers            ; 66    ;
;     -- I/O registers                        ; 0     ;
;                                             ;       ;
; I/O pins                                    ; 5     ;
; Maximum fan-out node                        ; clk   ;
; Maximum fan-out                             ; 66    ;
; Total fan-out                               ; 385   ;
; Average fan-out                             ; 2.64  ;
+---------------------------------------------+-------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                        ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+------------------------------------+--------------+
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name                ; Library Name ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+------------------------------------+--------------+
; |fpga_uartrw               ; 75 (0)            ; 66 (0)       ; 0           ; 0            ; 0       ; 0         ; 5    ; 0            ; |fpga_uartrw                       ; work         ;
;    |uart_receiver:inst1|   ; 41 (41)           ; 36 (36)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |fpga_uartrw|uart_receiver:inst1   ; work         ;
;    |uart_transmitter:inst| ; 34 (34)           ; 30 (30)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |fpga_uartrw|uart_transmitter:inst ; work         ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+------------------------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+--------------------------------------------------------------------------------+
; Registers Removed During Synthesis                                             ;
+---------------------------------------+----------------------------------------+
; Register name                         ; Reason for Removal                     ;
+---------------------------------------+----------------------------------------+
; inst1/Baud8GeneratorAcc[1..2]         ; Merged with inst1/Baud8GeneratorAcc[0] ;
; inst1/Baud8GeneratorAcc[0]            ; Stuck at GND due to stuck port data_in ;
; Total Number of Removed Registers = 3 ;                                        ;
+---------------------------------------+----------------------------------------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 66    ;
; Number of registers using Synchronous Clear  ; 17    ;
; Number of registers using Synchronous Load   ; 1     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 25    ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                                                ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-------------------------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output                      ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-------------------------------------------------+
; 3:1                ; 3 bits    ; 6 LEs         ; 3 LEs                ; 3 LEs                  ; Yes        ; |fpga_uartrw|uart_receiver:inst1|bit_spacing[0] ;
; 3:1                ; 2 bits    ; 4 LEs         ; 0 LEs                ; 4 LEs                  ; Yes        ; |fpga_uartrw|uart_receiver:inst1|RxD_cnt_inv[0] ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-------------------------------------------------+


+--------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: uart_transmitter:inst ;
+-----------------------+----------+---------------------------------+
; Parameter Name        ; Value    ; Type                            ;
+-----------------------+----------+---------------------------------+
; ClkFrequency          ; 50000000 ; Untyped                         ;
; Baud                  ; 115200   ; Untyped                         ;
; RegisterInputData     ; 1        ; Untyped                         ;
; BaudGeneratorAccWidth ; 16       ; Untyped                         ;
+-----------------------+----------+---------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: uart_receiver:inst1 ;
+------------------------+----------+------------------------------+
; Parameter Name         ; Value    ; Type                         ;
+------------------------+----------+------------------------------+
; ClkFrequency           ; 50000000 ; Untyped                      ;
; Baud                   ; 115200   ; Untyped                      ;
; Baud8                  ; 921600   ; Signed Integer               ;
; Baud8GeneratorAccWidth ; 16       ; Untyped                      ;
+------------------------+----------+------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 7.1 Build 156 04/30/2007 SJ Full Version
    Info: Processing started: Wed May 07 10:09:49 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off fpga_uartrw -c fpga_uartrw
Info: Found 1 design units, including 1 entities, in source file fpga_receiver.v
    Info: Found entity 1: uart_receiver
Info: Found 1 design units, including 1 entities, in source file fpga_transmitter.v
    Info: Found entity 1: uart_transmitter
Info: Found 1 design units, including 1 entities, in source file fpga_uartrw.bdf
    Info: Found entity 1: fpga_uartrw
Info: Elaborating entity "fpga_uartrw" for the top level hierarchy
Info: Elaborating entity "uart_transmitter" for hierarchy "uart_transmitter:inst"
Warning (10230): Verilog HDL assignment warning at fpga_transmitter.v(21): truncated value with size 32 to match size of target (17)
Info: Elaborating entity "uart_receiver" for hierarchy "uart_receiver:inst1"
Warning (10036): Verilog HDL or VHDL warning at fpga_receiver.v(132): object "RxD_data_error" assigned a value but never read
Warning (10230): Verilog HDL assignment warning at fpga_receiver.v(21): truncated value with size 32 to match size of target (17)
Info: Duplicate registers merged to single register
    Info: Duplicate register "uart_receiver:inst1|Baud8GeneratorAcc[1]" merged to single register "uart_receiver:inst1|Baud8GeneratorAcc[0]"
    Info: Duplicate register "uart_receiver:inst1|Baud8GeneratorAcc[2]" merged to single register "uart_receiver:inst1|Baud8GeneratorAcc[0]"
Warning: Reduced register "uart_receiver:inst1|Baud8GeneratorAcc[0]" with stuck data_in port to stuck value GND
Info: Generated suppressed messages file D:/altera/71/jiangbinbin/fpga_uartrw/fpga_uartrw.map.smsg
Info: Implemented 96 device resources after synthesis - the final resource count might be different
    Info: Implemented 2 input pins
    Info: Implemented 3 output pins
    Info: Implemented 91 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 4 warnings
    Info: Allocated 139 megabytes of memory during processing
    Info: Processing ended: Wed May 07 10:09:52 2008
    Info: Elapsed time: 00:00:03


+------------------------------------------+
; Analysis & Synthesis Suppressed Messages ;
+------------------------------------------+
The suppressed messages can be found in D:/altera/71/jiangbinbin/fpga_uartrw/fpga_uartrw.map.smsg.