cmultipler.map.qmsg

复乘法器的FPGA实现

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.1 Build 201 11/27/2006 SJ Full Version " "Info: Version 6.1 Build 201 11/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue May 06 14:10:52 2008 " "Info: Processing started: Tue May 06 14:10:52 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off CMULTIPLER -c CMULTIPLER " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off CMULTIPLER -c CMULTIPLER" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Warning" "WSGN_FILE_IS_MISSING" "C:/altera/61/quartus/myq2projects/ddc/cmultipler/CMULTIPLER.v " "Warning: Can't analyze file -- file C:/altera/61/quartus/myq2projects/ddc/cmultipler/CMULTIPLER.v is missing" {  } {  } 0 0 "Can't analyze file -- file %1!s! is missing" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ADDSUB_16_0.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file ADDSUB_16_0.v" { { "Info" "ISGN_ENTITY_NAME" "1 ADDSUB_16_0 " "Info: Found entity 1: ADDSUB_16_0" {  } { { "ADDSUB_16_0.v" "" { Text "C:/altera/61/quartus/myq2projects/ddc/cmultipler/ADDSUB_16_0.v" 2 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ADDSUB.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file ADDSUB.v" { { "Info" "ISGN_ENTITY_NAME" "1 ADDSUB " "Info: Found entity 1: ADDSUB" {  } { { "ADDSUB.v" "" { Text "C:/altera/61/quartus/myq2projects/ddc/cmultipler/ADDSUB.v" 36 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "MULTP.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file MULTP.v" { { "Info" "ISGN_ENTITY_NAME" "1 MULTP " "Info: Found entity 1: MULTP" {  } { { "MULTP.v" "" { Text "C:/altera/61/quartus/myq2projects/ddc/cmultipler/MULTP.v" 36 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "CMULTIPLER_tb.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file CMULTIPLER_tb.v" { { "Info" "ISGN_ENTITY_NAME" "1 CMULTIPLEX_tb " "Info: Found entity 1: CMULTIPLEX_tb" {  } { { "CMULTIPLER_tb.v" "" { Text "C:/altera/61/quartus/myq2projects/ddc/cmultipler/CMULTIPLER_tb.v" 2 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "CMULTIPLEX.v 1 1 " "Warning: Using design file CMULTIPLEX.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 CMULTIPLEX " "Info: Found entity 1: CMULTIPLEX" {  } { { "CMULTIPLEX.v" "" { Text "C:/altera/61/quartus/myq2projects/ddc/cmultipler/CMULTIPLEX.v" 2 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "CMULTIPLEX " "Info: Elaborating entity \"CMULTIPLEX\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ADDSUB_16_0 ADDSUB_16_0:add1 " "Info: Elaborating entity \"ADDSUB_16_0\" for hierarchy \"ADDSUB_16_0:add1\"" {  } { { "CMULTIPLEX.v" "add1" { Text "C:/altera/61/quartus/myq2projects/ddc/cmultipler/CMULTIPLEX.v" 58 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ADDSUB ADDSUB_16_0:add1\|ADDSUB:addsub " "Info: Elaborating entity \"ADDSUB\" for hierarchy \"ADDSUB_16_0:add1\|ADDSUB:addsub\"" {  } { { "ADDSUB_16_0.v" "addsub" { Text "C:/altera/61/quartus/myq2projects/ddc/cmultipler/ADDSUB_16_0.v" 29 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../../libraries/megafunctions/lpm_add_sub.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../../libraries/megafunctions/lpm_add_sub.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_add_sub " "Info: Found entity 1: lpm_add_sub" {  } { { "lpm_add_sub.tdf" "" { Text "c:/altera/61/quartus/libraries/megafunctions/lpm_add_sub.tdf" 102 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_add_sub ADDSUB_16_0:add1\|ADDSUB:addsub\|lpm_add_sub:lpm_add_sub_component " "Info: Elaborating entity \"lpm_add_sub\" for hierarchy \"ADDSUB_16_0:add1\|ADDSUB:addsub\|lpm_add_sub:lpm_add_sub_component\"" {  } { { "ADDSUB.v" "lpm_add_sub_component" { Text "C:/altera/61/quartus/myq2projects/ddc/cmultipler/ADDSUB.v" 64 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "ADDSUB_16_0:add1\|ADDSUB:addsub\|lpm_add_sub:lpm_add_sub_component " "Info: Elaborated megafunction instantiation \"ADDSUB_16_0:add1\|ADDSUB:addsub\|lpm_add_sub:lpm_add_sub_component\"" {  } { { "ADDSUB.v" "" { Text "C:/altera/61/quartus/myq2projects/ddc/cmultipler/ADDSUB.v" 64 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_4od.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_4od.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_4od " "Info: Found entity 1: add_sub_4od" {  } { { "db/add_sub_4od.tdf" "" { Text "C:/altera/61/quartus/myq2projects/ddc/cmultipler/db/add_sub_4od.tdf" 25 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "add_sub_4od ADDSUB_16_0:add1\|ADDSUB:addsub\|lpm_add_sub:lpm_add_sub_component\|add_sub_4od:auto_generated " "Info: Elaborating entity \"add_sub_4od\" for hierarchy \"ADDSUB_16_0:add1\|ADDSUB:addsub\|lpm_add_sub:lpm_add_sub_component\|add_sub_4od:auto_generated\"" {  } { { "lpm_add_sub.tdf" "auto_generated" { Text "c:/altera/61/quartus/libraries/megafunctions/lpm_add_sub.tdf" 119 3 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "MULTP MULTP:mult1 " "Info: Elaborating entity \"MULTP\" for hierarchy \"MULTP:mult1\"" {  } { { "CMULTIPLEX.v" "mult1" { Text "C:/altera/61/quartus/myq2projects/ddc/cmultipler/CMULTIPLEX.v" 97 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../../libraries/megafunctions/lpm_mult.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../../libraries/megafunctions/lpm_mult.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_mult " "Info: Found entity 1: lpm_mult" {  } { { "lpm_mult.tdf" "" { Text "c:/altera/61/quartus/libraries/megafunctions/lpm_mult.tdf" 284 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_mult MULTP:mult1\|lpm_mult:lpm_mult_component " "Info: Elaborating entity \"lpm_mult\" for hierarchy \"MULTP:mult1\|lpm_mult:lpm_mult_component\"" {  } { { "MULTP.v" "lpm_mult_component" { Text "C:/altera/61/quartus/myq2projects/ddc/cmultipler/MULTP.v" 61 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "MULTP:mult1\|lpm_mult:lpm_mult_component " "Info: Elaborated megafunction instantiation \"MULTP:mult1\|lpm_mult:lpm_mult_component\"" {  } { { "MULTP.v" "" { Text "C:/altera/61/quartus/myq2projects/ddc/cmultipler/MULTP.v" 61 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mult_2su.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/mult_2su.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mult_2su " "Info: Found entity 1: mult_2su" {  } { { "db/mult_2su.tdf" "" { Text "C:/altera/61/quartus/myq2projects/ddc/cmultipler/db/mult_2su.tdf" 36 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mult_2su MULTP:mult1\|lpm_mult:lpm_mult_component\|mult_2su:auto_generated " "Info: Elaborating entity \"mult_2su\" for hierarchy \"MULTP:mult1\|lpm_mult:lpm_mult_component\|mult_2su:auto_generated\"" {  } { { "lpm_mult.tdf" "auto_generated" { Text "c:/altera/61/quartus/libraries/megafunctions/lpm_mult.tdf" 375 4 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "tempout\[16\] GND " "Warning: Pin \"tempout\[16\]\" stuck at GND" {  } { { "CMULTIPLEX.v" "" { Text "C:/altera/61/quartus/myq2projects/ddc/cmultipler/CMULTIPLEX.v" 9 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "tempout\[17\] GND " "Warning: Pin \"tempout\[17\]\" stuck at GND" {  } { { "CMULTIPLEX.v" "" { Text "C:/altera/61/quartus/myq2projects/ddc/cmultipler/CMULTIPLEX.v" 9 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "tempout\[18\] GND " "Warning: Pin \"tempout\[18\]\" stuck at GND" {  } { { "CMULTIPLEX.v" "" { Text "C:/altera/61/quartus/myq2projects/ddc/cmultipler/CMULTIPLEX.v" 9 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "tempout\[19\] GND " "Warning: Pin \"tempout\[19\]\" stuck at GND" {  } { { "CMULTIPLEX.v" "" { Text "C:/altera/61/quartus/myq2projects/ddc/cmultipler/CMULTIPLEX.v" 9 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "tempout\[20\] GND " "Warning: Pin \"tempout\[20\]\" stuck at GND" {  } { { "CMULTIPLEX.v" "" { Text "C:/altera/61/quartus/myq2projects/ddc/cmultipler/CMULTIPLEX.v" 9 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "tempout\[21\] GND " "Warning: Pin \"tempout\[21\]\" stuck at GND" {  } { { "CMULTIPLEX.v" "" { Text "C:/altera/61/quartus/myq2projects/ddc/cmultipler/CMULTIPLEX.v" 9 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "tempout\[22\] GND " "Warning: Pin \"tempout\[22\]\" stuck at GND" {  } { { "CMULTIPLEX.v" "" { Text "C:/altera/61/quartus/myq2projects/ddc/cmultipler/CMULTIPLEX.v" 9 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "tempout\[23\] GND " "Warning: Pin \"tempout\[23\]\" stuck at GND" {  } { { "CMULTIPLEX.v" "" { Text "C:/altera/61/quartus/myq2projects/ddc/cmultipler/CMULTIPLEX.v" 9 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "tempout\[24\] GND " "Warning: Pin \"tempout\[24\]\" stuck at GND" {  } { { "CMULTIPLEX.v" "" { Text "C:/altera/61/quartus/myq2projects/ddc/cmultipler/CMULTIPLEX.v" 9 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "tempout\[25\] GND " "Warning: Pin \"tempout\[25\]\" stuck at GND" {  } { { "CMULTIPLEX.v" "" { Text "C:/altera/61/quartus/myq2projects/ddc/cmultipler/CMULTIPLEX.v" 9 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "tempout\[26\] GND " "Warning: Pin \"tempout\[26\]\" stuck at GND" {  } { { "CMULTIPLEX.v" "" { Text "C:/altera/61/quartus/myq2projects/ddc/cmultipler/CMULTIPLEX.v" 9 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "tempout\[27\] GND " "Warning: Pin \"tempout\[27\]\" stuck at GND" {  } { { "CMULTIPLEX.v" "" { Text "C:/altera/61/quartus/myq2projects/ddc/cmultipler/CMULTIPLEX.v" 9 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "tempout\[28\] GND " "Warning: Pin \"tempout\[28\]\" stuck at GND" {  } { { "CMULTIPLEX.v" "" { Text "C:/altera/61/quartus/myq2projects/ddc/cmultipler/CMULTIPLEX.v" 9 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "tempout\[29\] GND " "Warning: Pin \"tempout\[29\]\" stuck at GND" {  } { { "CMULTIPLEX.v" "" { Text "C:/altera/61/quartus/myq2projects/ddc/cmultipler/CMULTIPLEX.v" 9 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "tempout\[30\] GND " "Warning: Pin \"tempout\[30\]\" stuck at GND" {  } { { "CMULTIPLEX.v" "" { Text "C:/altera/61/quartus/myq2projects/ddc/cmultipler/CMULTIPLEX.v" 9 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "tempout\[31\] GND " "Warning: Pin \"tempout\[31\]\" stuck at GND" {  } { { "CMULTIPLEX.v" "" { Text "C:/altera/61/quartus/myq2projects/ddc/cmultipler/CMULTIPLEX.v" 9 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0}  } {  } 0 0 "Output pins are stuck at VCC or GND" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "399 " "Info: Implemented 399 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "67 " "Info: Implemented 67 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "64 " "Info: Implemented 64 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "262 " "Info: Implemented 262 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0} { "Info" "ISCL_SCL_TM_DSP_ELEM" "6 " "Info: Implemented 6 DSP elements" {  } {  } 0 0 "Implemented %1!d! DSP elements" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 19 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 19 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "133 " "Info: Allocated 133 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Tue May 06 14:10:55 2008 " "Info: Processing ended: Tue May 06 14:10:55 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}