cmultipler.fit.summary

来自「复乘法器的FPGA实现」· SUMMARY 代码 · 共 18 行

Fitter Status : Successful - Tue May 06 14:11:11 2008
Quartus II Version : 6.1 Build 201 11/27/2006 SJ Full Version
Revision Name : CMULTIPLER
Top-level Entity Name : CMULTIPLEX
Family : Stratix II
Device : EP2S15F484C3
Timing Models : Final
Logic utilization : 2 %
    Combinational ALUTs : 162 / 12,480 ( 1 % )
    Dedicated logic registers : 160 / 12,480 ( 1 % )
Total registers : 160
Total pins : 131 / 343 ( 38 % )
Total virtual pins : 0
Total block memory bits : 0 / 419,328 ( 0 % )
DSP block 9-bit elements : 6 / 96 ( 6 % )
Total PLLs : 0 / 6 ( 0 % )
Total DLLs : 0 / 2 ( 0 % )