addsub_16_0.v

来自「复乘法器的FPGA实现」· Verilog 代码 · 共 31 行

`timescale 1 ps / 1 ps
module ADDSUB_16_0(
	add_sub,
	dataa,
	datab,
	result);
	
	parameter word_in_size = 16;
	
	input	 add_sub;
	input	[word_in_size-1:0]  dataa;
	input	[word_in_size-1:0]  datab;
	output	[word_in_size-1:0]  result;
	
	wire [word_in_size-1:0] tmp; 
	wire [word_in_size:0] da,db;
	wire [word_in_size:0] rt;

	assign da[word_in_size-1:0] = dataa;
	assign da[word_in_size] = dataa[word_in_size-1];
	assign db[word_in_size-1:0] = datab;
	assign db[word_in_size] = datab[word_in_size-1];
	assign tmp = rt[word_in_size]?16'b1000000000000000:16'b0111111111111111;
	assign result = rt[word_in_size]^rt[word_in_size-1]?tmp:rt[word_in_size-1:0];
	ADDSUB addsub(
	.add_sub(add_sub),
	.dataa(da),
	.datab(db),
	.result(rt));

endmodule