cmultipler.map.summary

来自「复乘法器的FPGA实现」· SUMMARY 代码 · 共 16 行

Analysis & Synthesis Status : Successful - Tue May 06 14:10:55 2008
Quartus II Version : 6.1 Build 201 11/27/2006 SJ Full Version
Revision Name : CMULTIPLER
Top-level Entity Name : CMULTIPLEX
Family : Stratix II
Logic utilization : N/A
    Combinational ALUTs : 162
    Dedicated logic registers : 160
Total registers : 160
Total pins : 131
Total virtual pins : 0
Total block memory bits : 0
DSP block 9-bit elements : 6
Total PLLs : 0
Total DLLs : 0