cmultipler_tb.v

来自「复乘法器的FPGA实现」· Verilog 代码 · 共 52 行

`timescale 1 ns / 1 ns
module CMULTIPLEX_tb; 
reg clk;
reg clkena; 
reg reset;
reg [15:0] ia;
reg [15:0] qa;
reg [15:0] ib;
reg [15:0] qb;
wire [31:0] tempout;
wire [15:0] iout;
wire [15:0] qout;
CMULTIPLEX UUT(
.clk(clk), 
.clkena(clkena), 
.reset(reset), 
.ia(ia), 
.qa(qa), 
.ib(ib), 
.qb(qb),
.tempout(tempout), 
.iout(iout), 
.qout(qout)
);

initial // Clock generator
begin
  clk = 0;
  forever #10 clk = !clk;
end 


initial// Test stimulus
begin
  reset = 1;
  #10 reset = 0;
  clkena = 1;
  #40 clk = 0;
  #100 clkena = 0; 
  ia = 2;
  qa = 3;
  ib = 5;
  qb = 6;
  #20 ia = 2;qa = -3;ib = 5;qb = 6;
  #40 ia = 2;qa = 3;ib = -5;qb = 6;
  #80 ia = 2;qa = 3;ib = 5;qb = -6;
  
end
endmodule