rev.vhdl

xilinx环境下开发vhdl语言串行接口设计

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity rev is
    Port ( clrn: in std_logic;
           clktr : in std_logic;
           rxd : in std_logic;
           rdata : out std_logic_vector(7 downto 0);
           rcving : out std_logic;
           done_rcving : out std_logic;
           enclk : out std_logic);
end rev;

architecture main of rev is
  signal 	startm : std_logic;
  signal    count	: std_logic_vector(3 downto 0);

begin
    process(rxd,clrn)
     begin
	 if 	clrn='0'  then 
			 startm<='0';
	  else
	   	 startm<=not rxd;
      end if;
    end process;

	process(startm,clrn)
	 begin
	  if	clrn='0'  then
		  enclk<='0';
	  elsif  startm='1' and   startm'event then 
	      enclk<='1';
       end if;
     end process;

    
	process(clrn,clktr)
	 begin	 
	  if clrn='0'   then 
	     count<="0000";
	  elsif    clktr='0' and clktr'event    then 
		    count<=count+1;
		    if count="1010" then
				  count<="0000";		     
		    end if;

     end if;
   end process;

	  process(clrn,count)
	  begin
	   if clrn='0'  then
		    rdata<="00000000";
			 rcving<='0';
			 done_rcving<='0';
      else
		    case count is
			    when  "0000" =>  NULL;
			    when  "0001" =>  rdata(0)<=rxd;	   rcving<='1';
				 when  "0010" =>  rdata(1)<=rxd; 
     			 when  "0011" =>  rdata(2)<=rxd;
				 when  "0100" =>  rdata(3)<=rxd; 
				 when  "0101" =>  rdata(4)<=rxd;
				 when  "0110" =>  rdata(5)<=rxd; 
				 when  "0111" =>  rdata(6)<=rxd;
				 when  "1000" =>  rdata(7)<=rxd;
				 when others  =>    rcving<='0';  done_rcving<='1';
          end case;
		 end if;
		end process;

end main;