test2.vhw

来自「xilinx环境下开发vhdl语言串行接口设计」· VHW 代码 · 共 231 行

-- E:\AA
-- VHDL Test Bench created by
-- HDL Bencher 6.1i
-- Fri Oct 31 13:45:57 2008
-- 
-- Notes:
-- 1) This testbench has been automatically generated from
--   your Test Bench Waveform
-- 2) To use this as a user modifiable testbench do the following:
--   - Save it as a file with a .vhd extension (i.e. File->Save As...)
--   - Add it to your project as a testbench source (i.e. Project->Add Source...)
-- 

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_TEXTIO.ALL;
USE STD.TEXTIO.ALL;

ENTITY test2 IS
END test2;

ARCHITECTURE testbench_arch OF test2 IS
-- If you get a compiler error on the following line,
-- from the menu do Options->Configuration select VHDL 87
FILE RESULTS: TEXT OPEN WRITE_MODE IS "results.txt";
	COMPONENT rev
		PORT (
			clrn : In  std_logic;
			clktr : In  std_logic;
			rxd : In  std_logic;
			rdata : Out  std_logic_vector (7 DOWNTO 0);
			rcving : Out  std_logic;
			done_rcving : Out  std_logic;
			enclk : Out  std_logic
		);
	END COMPONENT;

	SIGNAL clrn : std_logic;
	SIGNAL clktr : std_logic;
	SIGNAL rxd : std_logic;
	SIGNAL rdata : std_logic_vector (7 DOWNTO 0);
	SIGNAL rcving : std_logic;
	SIGNAL done_rcving : std_logic;
	SIGNAL enclk : std_logic;

BEGIN
	UUT : rev
	PORT MAP (
		clrn => clrn,
		clktr => clktr,
		rxd => rxd,
		rdata => rdata,
		rcving => rcving,
		done_rcving => done_rcving,
		enclk => enclk
	);

	PROCESS -- clock process for clktr,
	BEGIN
		CLOCK_LOOP : LOOP
		clktr <= transport '0';
		WAIT FOR 10 ns;
		clktr <= transport '1';
		WAIT FOR 10 ns;
		WAIT FOR 40 ns;
		clktr <= transport '0';
		WAIT FOR 40 ns;
		END LOOP CLOCK_LOOP;
	END PROCESS;

	PROCESS   -- Process for clktr
		VARIABLE TX_OUT : LINE;
		VARIABLE TX_ERROR : INTEGER := 0;

		PROCEDURE CHECK_rdata(
			next_rdata : std_logic_vector (7 DOWNTO 0);
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			-- If compiler error ("/=" is ambiguous) occurs in the next line of code
			-- change compiler settings to use explicit declarations only
			IF (rdata /= next_rdata) THEN 
				STD.TEXTIO.write(TX_LOC,string'("Error at time="));
				STD.TEXTIO.write(TX_LOC, TX_TIME);
				STD.TEXTIO.write(TX_LOC,string'("ns rdata="));
				IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, rdata);
				STD.TEXTIO.write(TX_LOC, string'(", Expected = "));
				IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_rdata);
				STD.TEXTIO.write(TX_LOC, string'(" "));
				TX_STR(TX_LOC.all'range) := TX_LOC.all;
				STD.TEXTIO.writeline(results, TX_LOC);
				STD.TEXTIO.Deallocate(TX_LOC);
				ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
				TX_ERROR := TX_ERROR + 1;
			END IF;
		END;

		PROCEDURE CHECK_rcving(
			next_rcving : std_logic;
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			-- If compiler error ("/=" is ambiguous) occurs in the next line of code
			-- change compiler settings to use explicit declarations only
			IF (rcving /= next_rcving) THEN 
				STD.TEXTIO.write(TX_LOC,string'("Error at time="));
				STD.TEXTIO.write(TX_LOC, TX_TIME);
				STD.TEXTIO.write(TX_LOC,string'("ns rcving="));
				IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, rcving);
				STD.TEXTIO.write(TX_LOC, string'(", Expected = "));
				IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_rcving);
				STD.TEXTIO.write(TX_LOC, string'(" "));
				TX_STR(TX_LOC.all'range) := TX_LOC.all;
				STD.TEXTIO.writeline(results, TX_LOC);
				STD.TEXTIO.Deallocate(TX_LOC);
				ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
				TX_ERROR := TX_ERROR + 1;
			END IF;
		END;

		PROCEDURE CHECK_done_rcving(
			next_done_rcving : std_logic;
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			-- If compiler error ("/=" is ambiguous) occurs in the next line of code
			-- change compiler settings to use explicit declarations only
			IF (done_rcving /= next_done_rcving) THEN 
				STD.TEXTIO.write(TX_LOC,string'("Error at time="));
				STD.TEXTIO.write(TX_LOC, TX_TIME);
				STD.TEXTIO.write(TX_LOC,string'("ns done_rcving="));
				IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, done_rcving);
				STD.TEXTIO.write(TX_LOC, string'(", Expected = "));
				IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_done_rcving);
				STD.TEXTIO.write(TX_LOC, string'(" "));
				TX_STR(TX_LOC.all'range) := TX_LOC.all;
				STD.TEXTIO.writeline(results, TX_LOC);
				STD.TEXTIO.Deallocate(TX_LOC);
				ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
				TX_ERROR := TX_ERROR + 1;
			END IF;
		END;

		PROCEDURE CHECK_enclk(
			next_enclk : std_logic;
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			-- If compiler error ("/=" is ambiguous) occurs in the next line of code
			-- change compiler settings to use explicit declarations only
			IF (enclk /= next_enclk) THEN 
				STD.TEXTIO.write(TX_LOC,string'("Error at time="));
				STD.TEXTIO.write(TX_LOC, TX_TIME);
				STD.TEXTIO.write(TX_LOC,string'("ns enclk="));
				IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, enclk);
				STD.TEXTIO.write(TX_LOC, string'(", Expected = "));
				IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_enclk);
				STD.TEXTIO.write(TX_LOC, string'(" "));
				TX_STR(TX_LOC.all'range) := TX_LOC.all;
				STD.TEXTIO.writeline(results, TX_LOC);
				STD.TEXTIO.Deallocate(TX_LOC);
				ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
				TX_ERROR := TX_ERROR + 1;
			END IF;
		END;

		BEGIN
		-- --------------------
		rxd <= transport '1';
		clrn <= transport '0';
		-- --------------------
		WAIT FOR 100 ns; -- Time=100 ns
		clrn <= transport '1';
		-- --------------------
		WAIT FOR 100 ns; -- Time=200 ns
		rxd <= transport '1';
		-- --------------------
		WAIT FOR 100 ns; -- Time=300 ns
		rxd <= transport '0';
		-- --------------------
		WAIT FOR 100 ns; -- Time=400 ns
		rxd <= transport '1';
		-- --------------------
		WAIT FOR 100 ns; -- Time=500 ns
		rxd <= transport '0';
		-- --------------------
		WAIT FOR 200 ns; -- Time=700 ns
		rxd <= transport '1';
		-- --------------------
		WAIT FOR 200 ns; -- Time=900 ns
		rxd <= transport '0';
		-- --------------------
		WAIT FOR 500 ns; -- Time=1400 ns
		rxd <= transport '1';
		-- --------------------
		WAIT FOR 860 ns; -- Time=2260 ns
		-- --------------------

		IF (TX_ERROR = 0) THEN 
			STD.TEXTIO.write(TX_OUT,string'("No errors or warnings"));
			STD.TEXTIO.writeline(results, TX_OUT);
			ASSERT (FALSE) REPORT
				"Simulation successful (not a failure).  No problems detected. "
				SEVERITY FAILURE;
		ELSE
			STD.TEXTIO.write(TX_OUT, TX_ERROR);
			STD.TEXTIO.write(TX_OUT, string'(
				" errors found in simulation"));
			STD.TEXTIO.writeline(results, TX_OUT);
			ASSERT (FALSE) REPORT
				"Errors found during simulation"
				SEVERITY FAILURE;
		END IF;
	END PROCESS;
END testbench_arch;

CONFIGURATION rev_cfg OF test2 IS
	FOR testbench_arch
	END FOR;
END rev_cfg;