serial.syr

xilinx环境下开发vhdl语言串行接口设计

  Destination:       u5_Mtridata_iodb<5> (LATCH)
  Destination Clock: u5__n0082:O falling

  Data Path: rst to u5_Mtridata_iodb<5>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O            17   0.825   1.012  rst_IBUF (rst_IBUF)
     LUT3:I0->O            5   0.439   0.771  Ker38721 (N3874)
     LUT4:I3->O            1   0.439   0.517  Ker3810_SW115 (CHOICE281)
     LUT3:I2->O           31   0.439   1.085  Ker3810_SW118 (N3812)
     LUT3:I0->O            4   0.439   0.747  Ker38491 (N3851)
     LUT4:I3->O            1   0.439   0.000  u5__n00391 (u5__n0039)
     LDCP:D                    0.370          u5_Mtridata_iodb<4>
    ----------------------------------------
    Total                      7.523ns (3.390ns logic, 4.133ns route)
                                       (45.1% logic, 54.9% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET IN BEFORE for Clock 'u5__n0081:O'
Offset:              5.111ns (Levels of Logic = 4)
  Source:            rst (PAD)
  Destination:       u5_sclrn (LATCH)
  Destination Clock: u5__n0081:O falling

  Data Path: rst to u5_sclrn
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O            17   0.825   1.012  rst_IBUF (rst_IBUF)
     LUT3:I0->O            5   0.439   0.770  Ker38721 (N3874)
     LUT4:I1->O            7   0.439   0.816  Ker38921 (N3894)
     LUT2:I1->O            1   0.439   0.000  u5__n00331 (u5__n0033)
     LDCE:D                    0.370          u5_sclrn
    ----------------------------------------
    Total                      5.111ns (2.512ns logic, 2.599ns route)
                                       (49.1% logic, 50.9% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET IN BEFORE for Clock 'clk'
Offset:              2.646ns (Levels of Logic = 2)
  Source:            rst (PAD)
  Destination:       u1_clktr (FF)
  Destination Clock: clk rising

  Data Path: rst to u1_clktr
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O            17   0.825   1.012  rst_IBUF (rst_IBUF)
     LUT2:I0->O            1   0.439   0.000  u1_Mmux__n0003_Result1 (u1__n0003)
     FDCPE:D                   0.370          u1_clktr
    ----------------------------------------
    Total                      2.646ns (1.634ns logic, 1.012ns route)
                                       (61.8% logic, 38.2% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET IN BEFORE for Clock 'u3__n0049_SW134:O'
Offset:              3.602ns (Levels of Logic = 3)
  Source:            rst (PAD)
  Destination:       u3_txd (LATCH)
  Destination Clock: u3__n0049_SW134:O falling

  Data Path: rst to u3_txd
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O            17   0.825   1.012  rst_IBUF (rst_IBUF)
     LUT4:I0->O            1   0.439   0.517  u3__n0009134 (CHOICE337)
     LUT2:I1->O            1   0.439   0.000  u3__n0009146 (u3__n0009)
     LD:D                      0.370          u3_txd
    ----------------------------------------
    Total                      3.602ns (2.073ns logic, 1.529ns route)
                                       (57.5% logic, 42.5% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET IN BEFORE for Clock 'u3__n0048_SW129:O'
Offset:              3.602ns (Levels of Logic = 3)
  Source:            rst (PAD)
  Destination:       u3_done_xmitting (LATCH)
  Destination Clock: u3__n0048_SW129:O falling

  Data Path: rst to u3_done_xmitting
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O            17   0.825   1.012  rst_IBUF (rst_IBUF)
     LUT2:I1->O            1   0.439   0.517  u3__n0008_SW0 (N6507)
     LUT4:I0->O            1   0.439   0.000  u3__n0008 (u3__n0008)
     LD:D                      0.370          u3_done_xmitting
    ----------------------------------------
    Total                      3.602ns (2.073ns logic, 1.529ns route)
                                       (57.5% logic, 42.5% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET IN BEFORE for Clock 'u3__n0047:O'
Offset:              3.602ns (Levels of Logic = 3)
  Source:            rst (PAD)
  Destination:       u3_xmitting (LATCH)
  Destination Clock: u3__n0047:O falling

  Data Path: rst to u3_xmitting
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O            17   0.825   1.012  rst_IBUF (rst_IBUF)
     LUT2:I1->O            1   0.439   0.517  u3__n0006_SW0 (N6533)
     LUT4:I3->O            1   0.439   0.000  u3__n0006 (u3__n0006)
     LD:D                      0.370          u3_xmitting
    ----------------------------------------
    Total                      3.602ns (2.073ns logic, 1.529ns route)
                                       (57.5% logic, 42.5% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET IN BEFORE for Clock 'u4__n00121:O'
Offset:              2.057ns (Levels of Logic = 1)
  Source:            rxd (PAD)
  Destination:       u4_rdata_7 (LATCH)
  Destination Clock: u4__n00121:O falling

  Data Path: rxd to u4_rdata_7
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             9   0.825   0.862  rxd_IBUF (rxd_IBUF)
     LDC:D                     0.370          u4_rdata_7
    ----------------------------------------
    Total                      2.057ns (1.195ns logic, 0.862ns route)
                                       (58.1% logic, 41.9% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET IN BEFORE for Clock 'u4__n00141:O'
Offset:              2.057ns (Levels of Logic = 1)
  Source:            rxd (PAD)
  Destination:       u4_rdata_5 (LATCH)
  Destination Clock: u4__n00141:O falling

  Data Path: rxd to u4_rdata_5
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             9   0.825   0.862  rxd_IBUF (rxd_IBUF)
     LDC:D                     0.370          u4_rdata_5
    ----------------------------------------
    Total                      2.057ns (1.195ns logic, 0.862ns route)
                                       (58.1% logic, 41.9% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET IN BEFORE for Clock 'u4__n00191:O'
Offset:              2.057ns (Levels of Logic = 1)
  Source:            rxd (PAD)
  Destination:       u4_rdata_0 (LATCH)
  Destination Clock: u4__n00191:O falling

  Data Path: rxd to u4_rdata_0
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             9   0.825   0.862  rxd_IBUF (rxd_IBUF)
     LDC:D                     0.370          u4_rdata_0
    ----------------------------------------
    Total                      2.057ns (1.195ns logic, 0.862ns route)
                                       (58.1% logic, 41.9% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET IN BEFORE for Clock 'u4__n00181:O'
Offset:              2.057ns (Levels of Logic = 1)
  Source:            rxd (PAD)
  Destination:       u4_rdata_1 (LATCH)
  Destination Clock: u4__n00181:O falling

  Data Path: rxd to u4_rdata_1
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             9   0.825   0.862  rxd_IBUF (rxd_IBUF)
     LDC:D                     0.370          u4_rdata_1
    ----------------------------------------
    Total                      2.057ns (1.195ns logic, 0.862ns route)
                                       (58.1% logic, 41.9% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET IN BEFORE for Clock 'u4__n00171:O'
Offset:              2.057ns (Levels of Logic = 1)
  Source:            rxd (PAD)
  Destination:       u4_rdata_2 (LATCH)
  Destination Clock: u4__n00171:O falling

  Data Path: rxd to u4_rdata_2
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             9   0.825   0.862  rxd_IBUF (rxd_IBUF)
     LDC:D                     0.370          u4_rdata_2
    ----------------------------------------
    Total                      2.057ns (1.195ns logic, 0.862ns route)
                                       (58.1% logic, 41.9% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET IN BEFORE for Clock 'u4__n00161:O'
Offset:              2.057ns (Levels of Logic = 1)
  Source:            rxd (PAD)
  Destination:       u4_rdata_3 (LATCH)
  Destination Clock: u4__n00161:O falling

  Data Path: rxd to u4_rdata_3
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             9   0.825   0.862  rxd_IBUF (rxd_IBUF)
     LDC:D                     0.370          u4_rdata_3
    ----------------------------------------
    Total                      2.057ns (1.195ns logic, 0.862ns route)
                                       (58.1% logic, 41.9% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET IN BEFORE for Clock 'u4__n00131:O'
Offset:              2.057ns (Levels of Logic = 1)
  Source:            rxd (PAD)
  Destination:       u4_rdata_6 (LATCH)
  Destination Clock: u4__n00131:O falling

  Data Path: rxd to u4_rdata_6
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             9   0.825   0.862  rxd_IBUF (rxd_IBUF)
     LDC:D                     0.370          u4_rdata_6
    ----------------------------------------
    Total                      2.057ns (1.195ns logic, 0.862ns route)
                                       (58.1% logic, 41.9% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET IN BEFORE for Clock 'u4__n00151:O'
Offset:              2.057ns (Levels of Logic = 1)
  Source:            rxd (PAD)
  Destination:       u4_rdata_4 (LATCH)
  Destination Clock: u4__n00151:O falling

  Data Path: rxd to u4_rdata_4
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             9   0.825   0.862  rxd_IBUF (rxd_IBUF)
     LDC:D                     0.370          u4_rdata_4
    ----------------------------------------
    Total                      2.057ns (1.195ns logic, 0.862ns route)
                                       (58.1% logic, 41.9% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'u5__n0082:O'
Offset:              5.736ns (Levels of Logic = 1)
  Source:            u5_Mtridata_iodb<0> (LATCH)
  Destination:       iodb<0> (PAD)
  Source Clock:      u5__n0082:O falling

  Data Path: u5_Mtridata_iodb<0> to iodb<0>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LDCP:G->Q             2   0.674   0.701  u5_Mtridata_iodb<0> (u5_Mtridata_iodb<0>)
     IOBUF:I->IO               4.361          iodb_0_IOBUF (iodb<0>)
    ----------------------------------------
    Total                      5.736ns (5.035ns logic, 0.701ns route)
                                       (87.8% logic, 12.2% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'u5__n009142:O'
Offset:              5.483ns (Levels of Logic = 1)
  Source:            u5_Mtrien_iodb<0> (LATCH)
  Destination:       iodb<0> (PAD)
  Source Clock:      u5__n009142:O falling

  Data Path: u5_Mtrien_iodb<0> to iodb<0>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LD:G->Q               1   0.674   0.517  u5_Mtrien_iodb<0> (u5_Mtrien_iodb<0>)
     IOBUF:T->IO               4.292          iodb_0_IOBUF (iodb<0>)
    ----------------------------------------
    Total                      5.483ns (4.966ns logic, 0.517ns route)
                                       (90.6% logic, 9.4% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'u3__n0049_SW134:O'
Offset:              5.552ns (Levels of Logic = 1)
  Source:            u3_txd (LATCH)
  Destination:       txd (PAD)
  Source Clock:      u3__n0049_SW134:O falling

  Data Path: u3_txd to txd
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LD:G->Q               1   0.674   0.517  u3_txd (u3_txd)
     OBUF:I->O                 4.361          txd_OBUF (txd)
    ----------------------------------------
    Total                      5.552ns (5.035ns logic, 0.517ns route)
                                       (90.7% logic, 9.3% route)

=========================================================================
CPU : 4.92 / 5.47 s | Elapsed : 5.00 / 5.00 s
 
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Total memory usage is 93368 kilobytes