serial.syr

xilinx环境下开发vhdl语言串行接口设计

WARNING:Xst:382 - Register u5_Mtrien_iodb<3> is equivalent to u5_Mtrien_iodb<4>
WARNING:Xst:382 - Register u5_Mtrien_iodb<5> is equivalent to u5_Mtrien_iodb<4>
WARNING:Xst:382 - Register u5_Mtrien_iodb<7> is equivalent to u5_Mtrien_iodb<4>
WARNING:Xst:382 - Register u5_Mtrien_iodb<6> is equivalent to u5_Mtrien_iodb<3>
WARNING:Xst:382 - Register u5_Mtrien_iodb<0> is equivalent to u5_Mtrien_iodb<3>
WARNING:Xst:382 - Register u5_Mtrien_iodb<1> is equivalent to u5_Mtrien_iodb<3>
WARNING:Xst:382 - Register u5_Mtrien_iodb<2> is equivalent to u5_Mtrien_iodb<3>
WARNING:Xst:382 - Register u5_Mtrien_iodb<5> is equivalent to u5_Mtrien_iodb<3>
WARNING:Xst:382 - Register u5_Mtrien_iodb<7> is equivalent to u5_Mtrien_iodb<3>
WARNING:Xst:382 - Register u5_Mtrien_iodb<6> is equivalent to u5_Mtrien_iodb<2>
WARNING:Xst:382 - Register u5_Mtrien_iodb<0> is equivalent to u5_Mtrien_iodb<2>
WARNING:Xst:382 - Register u5_Mtrien_iodb<1> is equivalent to u5_Mtrien_iodb<2>
WARNING:Xst:382 - Register u5_Mtrien_iodb<5> is equivalent to u5_Mtrien_iodb<2>
WARNING:Xst:382 - Register u5_Mtrien_iodb<7> is equivalent to u5_Mtrien_iodb<2>
WARNING:Xst:382 - Register u5_Mtrien_iodb<6> is equivalent to u5_Mtrien_iodb<1>
WARNING:Xst:382 - Register u5_Mtrien_iodb<0> is equivalent to u5_Mtrien_iodb<1>
WARNING:Xst:382 - Register u5_Mtrien_iodb<5> is equivalent to u5_Mtrien_iodb<1>
WARNING:Xst:382 - Register u5_Mtrien_iodb<7> is equivalent to u5_Mtrien_iodb<1>
WARNING:Xst:382 - Register u5_Mtrien_iodb<6> is equivalent to u5_Mtrien_iodb<0>
WARNING:Xst:382 - Register u5_Mtrien_iodb<5> is equivalent to u5_Mtrien_iodb<0>
WARNING:Xst:382 - Register u5_Mtrien_iodb<7> is equivalent to u5_Mtrien_iodb<0>
WARNING:Xst:382 - Register u5_Mtrien_iodb<6> is equivalent to u5_Mtrien_iodb<5>
WARNING:Xst:382 - Register u5_Mtrien_iodb<7> is equivalent to u5_Mtrien_iodb<5>
WARNING:Xst:382 - Register u5_Mtrien_iodb<7> is equivalent to u5_Mtrien_iodb<6>

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : serial.ngr
Top Level Output File Name         : serial
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 17

Macro Statistics :
# Registers                        : 5
#      1-bit register              : 3
#      4-bit register              : 2
# Counters                         : 2
#      8-bit up counter            : 2
# Multiplexers                     : 4
#      2-to-1 multiplexer          : 4
# Tristates                        : 8
#      1-bit tristate buffer       : 8

Cell Usage :
# BELS                             : 158
#      GND                         : 1
#      LUT1                        : 5
#      LUT2                        : 34
#      LUT2_D                      : 2
#      LUT3                        : 10
#      LUT3_L                      : 6
#      LUT4                        : 67
#      MUXCY                       : 16
#      VCC                         : 1
#      XORCY                       : 16
# FlipFlops/Latches                : 67
#      FDC                         : 5
#      FDC_1                       : 4
#      FDCE                        : 2
#      FDCPE                       : 18
#      LD                          : 13
#      LDC                         : 8
#      LDCE                        : 9
#      LDCP                        : 8
# IO Buffers                       : 17
#      IBUF                        : 8
#      IOBUF                       : 8
#      OBUF                        : 1
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2v2000bf957-4 

 Number of Slices:                      76  out of  10752     0%  
 Number of Slice Flip Flops:            67  out of  21504     0%  
 Number of 4 input LUTs:               124  out of  21504     0%  
 Number of bonded IOBs:                 17  out of    624     2%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk                                | IBUF                   | 20    |
u1_clktr:Q                         | NONE                   | 4     |
u2_clktr:Q                         | NONE                   | 4     |
u5__n0091(u5__n009142:O)           | NONE(*)(u5_Mtrien_iodb<1>)| 8     |
npreq                              | IBUF                   | 8     |
u5__n0082(u5__n0082:O)             | NONE(*)(u5_Mtridata_iodb<1>)| 8     |
u5__n0081(u5__n0081:O)             | NONE(*)(u5_sclrn)      | 1     |
u3__n0049(u3__n0049_SW134:O)       | NONE(*)(u3_txd)        | 1     |
u3__n0048(u3__n0048_SW129:O)       | NONE(*)(u3_done_xmitting)| 1     |
u3__n0047(u3__n0047:O)             | NONE(*)(u3_xmitting)   | 1     |
u4__n0056(u4__n00561:O)            | NONE(*)(u4_done_rcving)| 1     |
u4__n0055(u4__n00551:O)            | NONE(*)(u4_rcving)     | 1     |
u4__n0012(u4__n00121:O)            | NONE(*)(u4_rdata_7)    | 1     |
u4__n0014(u4__n00141:O)            | NONE(*)(u4_rdata_5)    | 1     |
u4__n0019(u4__n00191:O)            | NONE(*)(u4_rdata_0)    | 1     |
u4__n0018(u4__n00181:O)            | NONE(*)(u4_rdata_1)    | 1     |
u4__n0017(u4__n00171:O)            | NONE(*)(u4_rdata_2)    | 1     |
u4__n0016(u4__n00161:O)            | NONE(*)(u4_rdata_3)    | 1     |
u4__n0013(u4__n00131:O)            | NONE(*)(u4_rdata_6)    | 1     |
u4__n0015(u4__n00151:O)            | NONE(*)(u4_rdata_4)    | 1     |
u4_startm(u4_startm1:O)            | NONE(*)(u4_enclk)      | 1     |
-----------------------------------+------------------------+-------+
(*) These 17 clock signal(s) are generated by combinatorial logic,
and XST is not able to identify which are the primary clock signals.
Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic.

Timing Summary:
---------------
Speed Grade: -4

   Minimum period: 5.208ns (Maximum Frequency: 192.012MHz)
   Minimum input arrival time before clock: 8.433ns
   Maximum output required time after clock: 5.736ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'clk'
Delay:               5.208ns (Levels of Logic = 11)
  Source:            u2_count_6 (FF)
  Destination:       u2_count_7 (FF)
  Source Clock:      clk rising
  Destination Clock: clk rising

  Data Path: u2_count_6 to u2_count_7
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCPE:C->Q            2   0.568   0.701  u2_count_6 (u2_count_6)
     LUT4:I0->O            4   0.439   0.747  u2__n00017 (CHOICE392)
     LUT2_D:I0->LO         1   0.439   0.000  u2__n000121 (N7770)
     MUXCY:S->O            1   0.298   0.000  u2_count_inst_cy_0 (u2_count_inst_cy_0)
     MUXCY:CI->O           1   0.053   0.000  u2_count_inst_cy_1 (u2_count_inst_cy_1)
     MUXCY:CI->O           1   0.053   0.000  u2_count_inst_cy_2 (u2_count_inst_cy_2)
     MUXCY:CI->O           1   0.053   0.000  u2_count_inst_cy_3 (u2_count_inst_cy_3)
     MUXCY:CI->O           1   0.053   0.000  u2_count_inst_cy_4 (u2_count_inst_cy_4)
     MUXCY:CI->O           1   0.053   0.000  u2_count_inst_cy_5 (u2_count_inst_cy_5)
     MUXCY:CI->O           1   0.053   0.000  u2_count_inst_cy_6 (u2_count_inst_cy_6)
     MUXCY:CI->O           0   0.053   0.000  u2_count_inst_cy_7 (u2_count_inst_cy_7)
     XORCY:CI->O           1   1.274   0.000  u2_count_inst_sum_7 (u2_count_inst_sum_7)
     FDCPE:D                   0.370          u2_count_7
    ----------------------------------------
    Total                      5.208ns (3.759ns logic, 1.449ns route)
                                       (72.2% logic, 27.8% route)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'u1_clktr:Q'
Delay:               2.332ns (Levels of Logic = 1)
  Source:            u3_count_1 (FF)
  Destination:       u3_count_1 (FF)
  Source Clock:      u1_clktr:Q rising
  Destination Clock: u1_clktr:Q rising

  Data Path: u3_count_1 to u3_count_1
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q             13   0.568   0.954  u3_count_1 (u3_count_1)
     LUT4:I2->O            1   0.439   0.000  u3_count_Mmux__n0001_Result<0>1 (u3_count__n0001<0>)
     FDC:D                     0.370          u3_count_0
    ----------------------------------------
    Total                      2.332ns (1.377ns logic, 0.954ns route)
                                       (59.1% logic, 40.9% route)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'u2_clktr:Q'
Delay:               2.378ns (Levels of Logic = 1)
  Source:            u4_count_0 (FF)
  Destination:       u4_count_1 (FF)
  Source Clock:      u2_clktr:Q falling
  Destination Clock: u2_clktr:Q falling

  Data Path: u4_count_0 to u4_count_1
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC_1:C->Q           16   0.568   1.000  u4_count_0 (u4_count_0)
     LUT4:I0->O            1   0.439   0.000  u4_count_Mmux__n0001_Result<1>1 (u4_count__n0001<1>)
     FDC_1:D                   0.370          u4_count_1
    ----------------------------------------
    Total                      2.378ns (1.377ns logic, 1.000ns route)
                                       (57.9% logic, 42.1% route)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'npreq'
Delay:               2.184ns (Levels of Logic = 1)
  Source:            u5_tdata_1 (LATCH)
  Destination:       u5_tdata_1 (LATCH)
  Source Clock:      npreq falling
  Destination Clock: npreq falling

  Data Path: u5_tdata_1 to u5_tdata_1
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LDCE:G->Q             2   0.674   0.701  u5_tdata_1 (u5_tdata_1)
     LUT4:I0->O            1   0.439   0.000  u5__n0032<1>1 (u5__n0032<1>)
     LDCE:D                    0.370          u5_tdata_1
    ----------------------------------------
    Total                      2.184ns (1.483ns logic, 0.701ns route)
                                       (67.9% logic, 32.1% route)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'u5__n0082:O'
Delay:               3.141ns (Levels of Logic = 2)
  Source:            u5_Mtridata_iodb<2> (LATCH)
  Destination:       u5_Mtridata_iodb<2> (LATCH)
  Source Clock:      u5__n0082:O falling
  Destination Clock: u5__n0082:O falling

  Data Path: u5_Mtridata_iodb<2> to u5_Mtridata_iodb<2>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LDCP:G->Q             2   0.674   0.702  u5_Mtridata_iodb<2> (u5_Mtridata_iodb<2>)
     LUT4:I1->O            1   0.439   0.517  u5__n00415 (CHOICE383)
     LUT4:I2->O            1   0.439   0.000  u5__n004117 (u5__n0041)
     LDCP:D                    0.370          u5_Mtridata_iodb<2>
    ----------------------------------------
    Total                      3.141ns (1.922ns logic, 1.219ns route)
                                       (61.2% logic, 38.8% route)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'u5__n0081:O'
Delay:               2.299ns (Levels of Logic = 1)
  Source:            u5_sclrn (LATCH)
  Destination:       u5_sclrn (LATCH)
  Source Clock:      u5__n0081:O falling
  Destination Clock: u5__n0081:O falling

  Data Path: u5_sclrn to u5_sclrn
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LDCE:G->Q             7   0.674   0.816  u5_sclrn (u5_sclrn)
     LUT2:I0->O            1   0.439   0.000  u5__n00331 (u5__n0033)
     LDCE:D                    0.370          u5_sclrn
    ----------------------------------------
    Total                      2.299ns (1.483ns logic, 0.816ns route)
                                       (64.5% logic, 35.5% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET IN BEFORE for Clock 'u5__n009142:O'
Offset:              6.336ns (Levels of Logic = 5)
  Source:            rst (PAD)
  Destination:       u5_Mtrien_iodb<4> (LATCH)
  Destination Clock: u5__n009142:O falling

  Data Path: rst to u5_Mtrien_iodb<4>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O            17   0.825   1.012  rst_IBUF (rst_IBUF)
     LUT3:I0->O            5   0.439   0.771  Ker38721 (N3874)
     LUT4:I3->O            1   0.439   0.517  Ker3810_SW115 (CHOICE281)
     LUT3:I2->O           31   0.439   1.085  Ker3810_SW118 (N3812)
     LUT4:I3->O            8   0.439   0.000  u5__n0058 (u5__n0058)
     LD:D                      0.370          u5_Mtrien_iodb<6>
    ----------------------------------------
    Total                      6.336ns (2.951ns logic, 3.385ns route)
                                       (46.6% logic, 53.4% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET IN BEFORE for Clock 'npreq'
Offset:              8.433ns (Levels of Logic = 7)
  Source:            rst (PAD)
  Destination:       u5_tdata_7 (LATCH)
  Destination Clock: npreq falling

  Data Path: rst to u5_tdata_7
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O            17   0.825   1.012  rst_IBUF (rst_IBUF)
     LUT3:I0->O            5   0.439   0.771  Ker38721 (N3874)
     LUT4:I3->O            1   0.439   0.517  Ker3810_SW115 (CHOICE281)
     LUT3:I2->O           31   0.439   1.085  Ker3810_SW118 (N3812)
     LUT4:I3->O            2   0.439   0.702  Ker37871 (N3789)
     LUT4:I1->O            1   0.439   0.517  u5__n0032<7>_SW0 (N7333)
     LUT4:I3->O            1   0.439   0.000  u5__n0032<7> (u5__n0032<7>)
     LDCE:D                    0.370          u5_tdata_7
    ----------------------------------------
    Total                      8.433ns (3.829ns logic, 4.604ns route)
                                       (45.4% logic, 54.6% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET IN BEFORE for Clock 'u5__n0082:O'
Offset:              7.523ns (Levels of Logic = 6)
  Source:            rst (PAD)