serial.syr

xilinx环境下开发vhdl语言串行接口设计

Release 6.2i - xst G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to __projnav
CPU : 0.00 / 0.28 s | Elapsed : 0.00 / 0.00 s
 
--> Parameter xsthdpdir set to ./xst
CPU : 0.00 / 0.28 s | Elapsed : 0.00 / 0.00 s
 
--> Reading design: serial.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
  5) Advanced HDL Synthesis
     5.1) HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : serial.prj
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO
Verilog Include Directory          : 

---- Target Parameters
Output File Name                   : serial
Output Format                      : NGC
Target Device                      : xc2v2000-4-bf957

---- Source Options
Top Module Name                    : serial
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
ROM Style                          : Auto
Mux Extraction                     : YES
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Resource Sharing                   : YES
Multiplier Style                   : auto
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 500
Add Generic Clock Buffer(BUFG)     : 0
Register Duplication               : YES
Equivalent register Removal        : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
Global Optimization                : AllClockNets
RTL Output                         : Yes
Write Timing Constraints           : NO
Hierarchy Separator                : _
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
Slice Utilization Ratio Delta      : 5

---- Other Options
lso                                : serial.lso
Read Cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES
Optimize Instantiated Primitives   : NO
tristate2logic                     : No

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file F:/aa/bps.vhdl in Library work.
Architecture main of Entity bps is up to date.
Compiling vhdl file F:/aa/xmit.vhdl in Library work.
Architecture main of Entity xmit is up to date.
Compiling vhdl file F:/aa/rev.vhdl in Library work.
Architecture main of Entity rev is up to date.
Compiling vhdl file F:/aa/ctrl.vhdl in Library work.
Architecture main of Entity ctrl is up to date.
Compiling vhdl file F:/aa/serial.vhdl in Library work.
Entity <serial> (Architecture <behavioral>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <serial> (Architecture <behavioral>).
Entity <serial> analyzed. Unit <serial> generated.

Analyzing Entity <bps> (Architecture <main>).
Entity <bps> analyzed. Unit <bps> generated.

Analyzing Entity <xmit> (Architecture <main>).
WARNING:Xst:819 - F:/aa/xmit.vhdl line 45: The following signals are missing in the process sensitivity list:
   tdata.
Entity <xmit> analyzed. Unit <xmit> generated.

Analyzing Entity <rev> (Architecture <main>).
WARNING:Xst:819 - F:/aa/rev.vhdl line 58: The following signals are missing in the process sensitivity list:
   rxd.
Entity <rev> analyzed. Unit <rev> generated.

Analyzing Entity <ctrl> (Architecture <main>).
WARNING:Xst:819 - F:/aa/ctrl.vhdl line 30: The following signals are missing in the process sensitivity list:
   ioab, iodb.
Entity <ctrl> analyzed. Unit <ctrl> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <ctrl>.
    Related source file is F:/aa/ctrl.vhdl.
WARNING:Xst:737 - Found 8-bit latch for signal <tdata>.
WARNING:Xst:737 - Found 1-bit latch for signal <sclrn>.
WARNING:Xst:736 - Found 1-bit latch for signal <Mtridata_iodb<7>> created at line 38.
WARNING:Xst:736 - Found 1-bit latch for signal <Mtridata_iodb<6>> created at line 38.
WARNING:Xst:736 - Found 1-bit latch for signal <Mtridata_iodb<5>> created at line 38.
WARNING:Xst:736 - Found 1-bit latch for signal <Mtridata_iodb<4>> created at line 38.
WARNING:Xst:736 - Found 1-bit latch for signal <Mtridata_iodb<3>> created at line 38.
WARNING:Xst:736 - Found 1-bit latch for signal <Mtridata_iodb<2>> created at line 38.
WARNING:Xst:736 - Found 1-bit latch for signal <Mtridata_iodb<1>> created at line 38.
WARNING:Xst:736 - Found 1-bit latch for signal <Mtridata_iodb<0>> created at line 38.
WARNING:Xst:736 - Found 1-bit latch for signal <Mtrien_iodb<7>> created at line 38.
WARNING:Xst:736 - Found 1-bit latch for signal <Mtrien_iodb<6>> created at line 38.
WARNING:Xst:736 - Found 1-bit latch for signal <Mtrien_iodb<5>> created at line 38.
WARNING:Xst:736 - Found 1-bit latch for signal <Mtrien_iodb<4>> created at line 38.
WARNING:Xst:736 - Found 1-bit latch for signal <Mtrien_iodb<3>> created at line 38.
WARNING:Xst:736 - Found 1-bit latch for signal <Mtrien_iodb<2>> created at line 38.
WARNING:Xst:736 - Found 1-bit latch for signal <Mtrien_iodb<1>> created at line 38.
WARNING:Xst:736 - Found 1-bit latch for signal <Mtrien_iodb<0>> created at line 38.
    Found 8-bit tristate buffer for signal <iodb>.
    Summary:
	inferred   8 Tristate(s).
Unit <ctrl> synthesized.


Synthesizing Unit <rev>.
    Related source file is F:/aa/rev.vhdl.
WARNING:Xst:737 - Found 1-bit latch for signal <rdata_7>.
WARNING:Xst:737 - Found 1-bit latch for signal <rdata_6>.
WARNING:Xst:737 - Found 1-bit latch for signal <rdata_5>.
WARNING:Xst:737 - Found 1-bit latch for signal <rdata_4>.
WARNING:Xst:737 - Found 1-bit latch for signal <rdata_3>.
WARNING:Xst:737 - Found 1-bit latch for signal <rdata_2>.
WARNING:Xst:737 - Found 1-bit latch for signal <rdata_1>.
WARNING:Xst:737 - Found 1-bit latch for signal <rdata_0>.
WARNING:Xst:737 - Found 1-bit latch for signal <rcving>.
WARNING:Xst:737 - Found 1-bit latch for signal <done_rcving>.
    Found 1-bit register for signal <enclk>.
    Found 4-bit up counter for signal <count>.
    Summary:
	inferred   1 Counter(s).
	inferred   1 D-type flip-flop(s).
Unit <rev> synthesized.


Synthesizing Unit <xmit>.
    Related source file is F:/aa/xmit.vhdl.
WARNING:Xst:737 - Found 1-bit latch for signal <xmitting>.
WARNING:Xst:737 - Found 1-bit latch for signal <done_xmitting>.
WARNING:Xst:737 - Found 1-bit latch for signal <txd>.
    Found 4-bit up counter for signal <count>.
    Summary:
	inferred   1 Counter(s).
Unit <xmit> synthesized.


Synthesizing Unit <bps>.
    Related source file is F:/aa/bps.vhdl.
    Found 1-bit register for signal <clktr>.
    Found 8-bit up counter for signal <count>.
    Found 1-bit register for signal <temp>.
    Found 1 1-bit 2-to-1 multiplexers.
    Summary:
	inferred   1 Counter(s).
	inferred   1 D-type flip-flop(s).
	inferred   1 Multiplexer(s).
Unit <bps> synthesized.


Synthesizing Unit <serial>.
    Related source file is F:/aa/serial.vhdl.
Unit <serial> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Counters                         : 4
 8-bit up counter                  : 2
 4-bit up counter                  : 2
# Registers                        : 5
 1-bit register                    : 5
# Latches                          : 31
 1-bit latch                       : 30
 8-bit latch                       : 1
# Multiplexers                     : 2
 1-bit 2-to-1 multiplexer          : 2
# Tristates                        : 8
 1-bit tristate buffer             : 8

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <serial> ...

Optimizing unit <bps> ...

Optimizing unit <xmit> ...

Optimizing unit <rev> ...
Loading device for application Xst from file '2v2000.nph' in environment C:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
WARNING:Xst:382 - Register u5_Mtrien_iodb<6> is equivalent to u5_Mtrien_iodb<4>
WARNING:Xst:382 - Register u5_Mtrien_iodb<0> is equivalent to u5_Mtrien_iodb<4>
WARNING:Xst:382 - Register u5_Mtrien_iodb<1> is equivalent to u5_Mtrien_iodb<4>
WARNING:Xst:382 - Register u5_Mtrien_iodb<2> is equivalent to u5_Mtrien_iodb<4>
WARNING:Xst:382 - Register u5_Mtrien_iodb<3> is equivalent to u5_Mtrien_iodb<4>
WARNING:Xst:382 - Register u5_Mtrien_iodb<5> is equivalent to u5_Mtrien_iodb<4>
WARNING:Xst:382 - Register u5_Mtrien_iodb<7> is equivalent to u5_Mtrien_iodb<4>
WARNING:Xst:382 - Register u5_Mtrien_iodb<6> is equivalent to u5_Mtrien_iodb<3>
WARNING:Xst:382 - Register u5_Mtrien_iodb<0> is equivalent to u5_Mtrien_iodb<3>
WARNING:Xst:382 - Register u5_Mtrien_iodb<1> is equivalent to u5_Mtrien_iodb<3>
WARNING:Xst:382 - Register u5_Mtrien_iodb<2> is equivalent to u5_Mtrien_iodb<3>
WARNING:Xst:382 - Register u5_Mtrien_iodb<5> is equivalent to u5_Mtrien_iodb<3>
WARNING:Xst:382 - Register u5_Mtrien_iodb<7> is equivalent to u5_Mtrien_iodb<3>
WARNING:Xst:382 - Register u5_Mtrien_iodb<6> is equivalent to u5_Mtrien_iodb<2>
WARNING:Xst:382 - Register u5_Mtrien_iodb<0> is equivalent to u5_Mtrien_iodb<2>
WARNING:Xst:382 - Register u5_Mtrien_iodb<1> is equivalent to u5_Mtrien_iodb<2>
WARNING:Xst:382 - Register u5_Mtrien_iodb<5> is equivalent to u5_Mtrien_iodb<2>
WARNING:Xst:382 - Register u5_Mtrien_iodb<7> is equivalent to u5_Mtrien_iodb<2>
WARNING:Xst:382 - Register u5_Mtrien_iodb<6> is equivalent to u5_Mtrien_iodb<1>
WARNING:Xst:382 - Register u5_Mtrien_iodb<0> is equivalent to u5_Mtrien_iodb<1>
WARNING:Xst:382 - Register u5_Mtrien_iodb<5> is equivalent to u5_Mtrien_iodb<1>
WARNING:Xst:382 - Register u5_Mtrien_iodb<7> is equivalent to u5_Mtrien_iodb<1>
WARNING:Xst:382 - Register u5_Mtrien_iodb<6> is equivalent to u5_Mtrien_iodb<0>
WARNING:Xst:382 - Register u5_Mtrien_iodb<5> is equivalent to u5_Mtrien_iodb<0>
WARNING:Xst:382 - Register u5_Mtrien_iodb<7> is equivalent to u5_Mtrien_iodb<0>
WARNING:Xst:382 - Register u5_Mtrien_iodb<6> is equivalent to u5_Mtrien_iodb<5>
WARNING:Xst:382 - Register u5_Mtrien_iodb<7> is equivalent to u5_Mtrien_iodb<5>
WARNING:Xst:382 - Register u5_Mtrien_iodb<7> is equivalent to u5_Mtrien_iodb<6>
WARNING:Xst:382 - Register u5_Mtrien_iodb<6> is equivalent to u5_Mtrien_iodb<4>
WARNING:Xst:382 - Register u5_Mtrien_iodb<0> is equivalent to u5_Mtrien_iodb<4>
WARNING:Xst:382 - Register u5_Mtrien_iodb<1> is equivalent to u5_Mtrien_iodb<4>
WARNING:Xst:382 - Register u5_Mtrien_iodb<2> is equivalent to u5_Mtrien_iodb<4>
WARNING:Xst:382 - Register u5_Mtrien_iodb<3> is equivalent to u5_Mtrien_iodb<4>
WARNING:Xst:382 - Register u5_Mtrien_iodb<5> is equivalent to u5_Mtrien_iodb<4>
WARNING:Xst:382 - Register u5_Mtrien_iodb<7> is equivalent to u5_Mtrien_iodb<4>
WARNING:Xst:382 - Register u5_Mtrien_iodb<6> is equivalent to u5_Mtrien_iodb<3>
WARNING:Xst:382 - Register u5_Mtrien_iodb<0> is equivalent to u5_Mtrien_iodb<3>
WARNING:Xst:382 - Register u5_Mtrien_iodb<1> is equivalent to u5_Mtrien_iodb<3>
WARNING:Xst:382 - Register u5_Mtrien_iodb<2> is equivalent to u5_Mtrien_iodb<3>
WARNING:Xst:382 - Register u5_Mtrien_iodb<5> is equivalent to u5_Mtrien_iodb<3>
WARNING:Xst:382 - Register u5_Mtrien_iodb<7> is equivalent to u5_Mtrien_iodb<3>
WARNING:Xst:382 - Register u5_Mtrien_iodb<6> is equivalent to u5_Mtrien_iodb<2>
WARNING:Xst:382 - Register u5_Mtrien_iodb<0> is equivalent to u5_Mtrien_iodb<2>
WARNING:Xst:382 - Register u5_Mtrien_iodb<1> is equivalent to u5_Mtrien_iodb<2>
WARNING:Xst:382 - Register u5_Mtrien_iodb<5> is equivalent to u5_Mtrien_iodb<2>
WARNING:Xst:382 - Register u5_Mtrien_iodb<7> is equivalent to u5_Mtrien_iodb<2>
WARNING:Xst:382 - Register u5_Mtrien_iodb<6> is equivalent to u5_Mtrien_iodb<1>
WARNING:Xst:382 - Register u5_Mtrien_iodb<0> is equivalent to u5_Mtrien_iodb<1>
WARNING:Xst:382 - Register u5_Mtrien_iodb<5> is equivalent to u5_Mtrien_iodb<1>
WARNING:Xst:382 - Register u5_Mtrien_iodb<7> is equivalent to u5_Mtrien_iodb<1>
WARNING:Xst:382 - Register u5_Mtrien_iodb<6> is equivalent to u5_Mtrien_iodb<0>
WARNING:Xst:382 - Register u5_Mtrien_iodb<5> is equivalent to u5_Mtrien_iodb<0>
WARNING:Xst:382 - Register u5_Mtrien_iodb<7> is equivalent to u5_Mtrien_iodb<0>
WARNING:Xst:382 - Register u5_Mtrien_iodb<6> is equivalent to u5_Mtrien_iodb<5>
WARNING:Xst:382 - Register u5_Mtrien_iodb<7> is equivalent to u5_Mtrien_iodb<5>
WARNING:Xst:382 - Register u5_Mtrien_iodb<7> is equivalent to u5_Mtrien_iodb<6>
Found area constraint ratio of 100 (+ 5) on block serial, actual ratio is 0.
WARNING:Xst:382 - Register u5_Mtrien_iodb<6> is equivalent to u5_Mtrien_iodb<4>
WARNING:Xst:382 - Register u5_Mtrien_iodb<0> is equivalent to u5_Mtrien_iodb<4>
WARNING:Xst:382 - Register u5_Mtrien_iodb<1> is equivalent to u5_Mtrien_iodb<4>
WARNING:Xst:382 - Register u5_Mtrien_iodb<2> is equivalent to u5_Mtrien_iodb<4>