ctrl.syr

xilinx环境下开发vhdl语言串行接口设计

#      LD                          : 8
#      LDCE                        : 9
#      LDCP                        : 8
# IO Buffers                       : 35
#      IBUF                        : 18
#      IOBUF                       : 8
#      OBUF                        : 9
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2v2000bf957-4 

 Number of Slices:                      43  out of  10752     0%  
 Number of Slice Flip Flops:            25  out of  21504     0%  
 Number of 4 input LUTs:                75  out of  21504     0%  
 Number of bonded IOBs:                 35  out of    624     5%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
N2413(_n009146:O)                  | NONE(*)(Mtrien_iodb<2>)| 8     |
npreq                              | IBUF                   | 8     |
_n0082(_n0082:O)                   | NONE(*)(Mtridata_iodb<4>)| 8     |
N2329(_n008121:O)                  | NONE(*)(sclrn)         | 1     |
-----------------------------------+------------------------+-------+
(*) These 3 clock signal(s) are generated by combinatorial logic,
and XST is not able to identify which are the primary clock signals.
Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic.

Timing Summary:
---------------
Speed Grade: -4

   Minimum period: 2.184ns (Maximum Frequency: 457.771MHz)
   Minimum input arrival time before clock: 8.850ns
   Maximum output required time after clock: 5.736ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'npreq'
Delay:               2.184ns (Levels of Logic = 1)
  Source:            tdata_2 (LATCH)
  Destination:       tdata_2 (LATCH)
  Source Clock:      npreq falling
  Destination Clock: npreq falling

  Data Path: tdata_2 to tdata_2
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LDCE:G->Q             2   0.674   0.701  tdata_2 (tdata_2)
     LUT4_L:I1->LO         1   0.439   0.000  _n0032<2>1 (_n0032<2>)
     LDCE:D                    0.370          tdata_2
    ----------------------------------------
    Total                      2.184ns (1.483ns logic, 0.701ns route)
                                       (67.9% logic, 32.1% route)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock '_n0082:O'
Delay:               2.184ns (Levels of Logic = 1)
  Source:            Mtridata_iodb<2> (LATCH)
  Destination:       Mtridata_iodb<2> (LATCH)
  Source Clock:      _n0082:O falling
  Destination Clock: _n0082:O falling

  Data Path: Mtridata_iodb<2> to Mtridata_iodb<2>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LDCP:G->Q             2   0.674   0.701  Mtridata_iodb<2> (Mtridata_iodb<2>)
     LUT4_L:I0->LO         1   0.439   0.000  _n004117 (_n0041)
     LDCP:D                    0.370          Mtridata_iodb<2>
    ----------------------------------------
    Total                      2.184ns (1.483ns logic, 0.701ns route)
                                       (67.9% logic, 32.1% route)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock '_n008121:O'
Delay:               2.184ns (Levels of Logic = 1)
  Source:            sclrn (LATCH)
  Destination:       sclrn (LATCH)
  Source Clock:      _n008121:O falling
  Destination Clock: _n008121:O falling

  Data Path: sclrn to sclrn
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LDCE:G->Q             2   0.674   0.701  sclrn (sclrn_OBUF)
     LUT4_L:I0->LO         1   0.439   0.000  _n0033 (_n0033)
     LDCE:D                    0.370          sclrn
    ----------------------------------------
    Total                      2.184ns (1.483ns logic, 0.701ns route)
                                       (67.9% logic, 32.1% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET IN BEFORE for Clock '_n009146:O'
Offset:              6.205ns (Levels of Logic = 5)
  Source:            rst (PAD)
  Destination:       Mtrien_iodb<4> (LATCH)
  Destination Clock: _n009146:O falling

  Data Path: rst to Mtrien_iodb<4>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O            10   0.825   0.885  rst_IBUF (rst_IBUF)
     LUT3:I1->O            4   0.439   0.747  Ker20631 (N2065)
     LUT4:I0->O            1   0.439   0.517  Ker1993_SW113 (CHOICE21)
     LUT3:I2->O           38   0.439   1.103  Ker1993_SW116 (N2275)
     LUT4:I2->O            8   0.439   0.000  _n0058 (_n0058)
     LD:D                      0.370          Mtrien_iodb<6>
    ----------------------------------------
    Total                      6.205ns (2.951ns logic, 3.254ns route)
                                       (47.6% logic, 52.4% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET IN BEFORE for Clock 'npreq'
Offset:              8.850ns (Levels of Logic = 7)
  Source:            rst (PAD)
  Destination:       tdata_2 (LATCH)
  Destination Clock: npreq falling

  Data Path: rst to tdata_2
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O            10   0.825   0.885  rst_IBUF (rst_IBUF)
     LUT3:I1->O            4   0.439   0.747  Ker20631 (N2065)
     LUT4:I0->O            1   0.439   0.517  Ker1993_SW113 (CHOICE21)
     LUT3:I2->O           38   0.439   1.103  Ker1993_SW116 (N2275)
     LUT3:I0->O            1   0.439   0.517  _n008112 (CHOICE30)
     LUT3:I2->O            1   0.439   0.518  _n008114 (CHOICE31)
     LUT4:I3->O            9   0.439   0.862  _n008121 (N2329)
     LDCE:GE                   0.240          tdata_1
    ----------------------------------------
    Total                      8.850ns (3.699ns logic, 5.151ns route)
                                       (41.8% logic, 58.2% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET IN BEFORE for Clock '_n0082:O'
Offset:              8.302ns (Levels of Logic = 7)
  Source:            rst (PAD)
  Destination:       Mtridata_iodb<3> (LATCH)
  Destination Clock: _n0082:O falling

  Data Path: rst to Mtridata_iodb<3>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O            10   0.825   0.885  rst_IBUF (rst_IBUF)
     LUT3:I1->O            4   0.439   0.747  Ker20631 (N2065)
     LUT4:I0->O            1   0.439   0.517  Ker1993_SW113 (CHOICE21)
     LUT3:I2->O           38   0.439   1.103  Ker1993_SW116 (N2275)
     LUT2:I0->O            2   0.439   0.702  _n00429 (CHOICE79)
     LUT4:I2->O            1   0.439   0.517  _n00405_SW0 (N2751)
     LUT4_L:I3->LO         1   0.439   0.000  _n004017 (_n0040)
     LDCP:D                    0.370          Mtridata_iodb<3>
    ----------------------------------------
    Total                      8.302ns (3.829ns logic, 4.473ns route)
                                       (46.1% logic, 53.9% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET IN BEFORE for Clock '_n008121:O'
Offset:              3.430ns (Levels of Logic = 3)
  Source:            ioab<0> (PAD)
  Destination:       sclrn (LATCH)
  Destination Clock: _n008121:O falling

  Data Path: ioab<0> to sclrn
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             8   0.825   0.840  ioab_0_IBUF (ioab_0_IBUF)
     LUT4:I0->O            1   0.439   0.517  _n0033_SW1 (N2775)
     LUT4_L:I2->LO         1   0.439   0.000  _n0033 (_n0033)
     LDCE:D                    0.370          sclrn
    ----------------------------------------
    Total                      3.430ns (2.073ns logic, 1.357ns route)
                                       (60.4% logic, 39.6% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock '_n0082:O'
Offset:              5.736ns (Levels of Logic = 1)
  Source:            Mtridata_iodb<0> (LATCH)
  Destination:       iodb<0> (PAD)
  Source Clock:      _n0082:O falling

  Data Path: Mtridata_iodb<0> to iodb<0>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LDCP:G->Q             2   0.674   0.701  Mtridata_iodb<0> (Mtridata_iodb<0>)
     IOBUF:I->IO               4.361          iodb_0_IOBUF (iodb<0>)
    ----------------------------------------
    Total                      5.736ns (5.035ns logic, 0.701ns route)
                                       (87.8% logic, 12.2% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock '_n009146:O'
Offset:              5.483ns (Levels of Logic = 1)
  Source:            Mtrien_iodb<0> (LATCH)
  Destination:       iodb<0> (PAD)
  Source Clock:      _n009146:O falling

  Data Path: Mtrien_iodb<0> to iodb<0>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LD:G->Q               1   0.674   0.517  Mtrien_iodb<0> (Mtrien_iodb<0>)
     IOBUF:T->IO               4.292          iodb_0_IOBUF (iodb<0>)
    ----------------------------------------
    Total                      5.483ns (4.966ns logic, 0.517ns route)
                                       (90.6% logic, 9.4% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock '_n008121:O'
Offset:              5.736ns (Levels of Logic = 1)
  Source:            sclrn (LATCH)
  Destination:       sclrn (PAD)
  Source Clock:      _n008121:O falling

  Data Path: sclrn to sclrn
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LDCE:G->Q             2   0.674   0.701  sclrn (sclrn_OBUF)
     OBUF:I->O                 4.361          sclrn_OBUF (sclrn)
    ----------------------------------------
    Total                      5.736ns (5.035ns logic, 0.701ns route)
                                       (87.8% logic, 12.2% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'npreq'
Offset:              5.736ns (Levels of Logic = 1)
  Source:            tdata_7 (LATCH)
  Destination:       tdata<7> (PAD)
  Source Clock:      npreq falling

  Data Path: tdata_7 to tdata<7>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LDCE:G->Q             2   0.674   0.701  tdata_7 (tdata_7)
     OBUF:I->O                 4.361          tdata_7_OBUF (tdata<7>)
    ----------------------------------------
    Total                      5.736ns (5.035ns logic, 0.701ns route)
                                       (87.8% logic, 12.2% route)

=========================================================================
CPU : 4.34 / 4.87 s | Elapsed : 4.00 / 4.00 s
 
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Total memory usage is 90296 kilobytes