__projnav.log

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   Maximum combinational path delay: No path found=========================================================================Completed process "Synthesize".

Project Navigator Auto-Make Log File-------------------------------------




Project Navigator Auto-Make Log File-------------------------------------



Project Navigator Auto-Make Log File-------------------------------------



Started process "Synthesize".=========================================================================*                          HDL Compilation                              *=========================================================================Compiling vhdl file E:/aa/bps.vhdl in Library work.ERROR:HDLParsers:1411 - E:/aa/bps.vhdl Line 27. Parameter clktr of mode out can not be associated with a formal parameter of mode in.--> Total memory usage is 48264 kilobytesERROR: XST failedProcess "Synthesize" did not complete.
Project Navigator Auto-Make Log File-------------------------------------



Started process "Synthesize".=========================================================================*                          HDL Compilation                              *=========================================================================Compiling vhdl file E:/aa/bps.vhdl in Library work.Entity <bps> (Architecture <main>) compiled.=========================================================================*                            HDL Analysis                               *=========================================================================Analyzing Entity <bps> (Architecture <main>).Entity <bps> analyzed. Unit <bps> generated.=========================================================================*                           HDL Synthesis                               *=========================================================================Synthesizing Unit <bps>.    Related source file is E:/aa/bps.vhdl.    Found 1-bit register for signal <clktr>.    Found 8-bit up counter for signal <count>.    Found 1-bit register for signal <temp>.    Summary:	inferred   1 Counter(s).	inferred   2 D-type flip-flop(s).Unit <bps> synthesized.=========================================================================*                       Advanced HDL Synthesis                          *=========================================================================Advanced RAM inference ...Advanced multiplier inference ...Dynamic shift register inference ...=========================================================================HDL Synthesis ReportMacro Statistics# Counters                         : 1 8-bit up counter                  : 1# Registers                        : 2 1-bit register                    : 2==================================================================================================================================================*                         Low Level Synthesis                           *=========================================================================Optimizing unit <bps> ...Loading device for application Xst from file '2v2000.nph' in environment C:/Xilinx.Mapping all equations...Building and optimizing final netlist ...Found area constraint ratio of 100 (+ 5) on block bps, actual ratio is 0.=========================================================================*                            Final Report                               *=========================================================================Device utilization summary:---------------------------Selected Device : 2v2000bf957-4  Number of Slices:                       8  out of  10752     0%   Number of Slice Flip Flops:            10  out of  21504     0%   Number of 4 input LUTs:                 9  out of  21504     0%   Number of bonded IOBs:                  3  out of    624     0%  =========================================================================TIMING REPORTClock Information:-----------------------------------------------------+------------------------+-------+Clock Signal                       | Clock buffer(FF name)  | Load  |-----------------------------------+------------------------+-------+clk                                | IBUF                   | 10    |-----------------------------------+------------------------+-------+Timing Summary:---------------Speed Grade: -4   Minimum period: 5.231ns (Maximum Frequency: 191.168MHz)   Minimum input arrival time before clock: 2.723ns   Maximum output required time after clock: 5.446ns   Maximum combinational path delay: No path found=========================================================================Completed process "Synthesize".

Project Navigator Auto-Make Log File-------------------------------------



Project Navigator Auto-Make Log File-------------------------------------


Started process "Synthesize".=========================================================================*                          HDL Compilation                              *=========================================================================Compiling vhdl file E:/aa/bps.vhdl in Library work.Architecture main of Entity bps is up to date.=========================================================================*                            HDL Analysis                               *=========================================================================Analyzing Entity <bps> (Architecture <main>).Entity <bps> analyzed. Unit <bps> generated.=========================================================================*                           HDL Synthesis                               *=========================================================================Synthesizing Unit <bps>.    Related source file is E:/aa/bps.vhdl.    Found 1-bit register for signal <clktr>.    Found 8-bit up counter for signal <count>.    Found 1-bit register for signal <temp>.    Summary:	inferred   1 Counter(s).	inferred   2 D-type flip-flop(s).Unit <bps> synthesized.=========================================================================*                       Advanced HDL Synthesis                          *=========================================================================Advanced RAM inference ...Advanced multiplier inference ...Dynamic shift register inference ...=========================================================================HDL Synthesis ReportMacro Statistics# Counters                         : 1 8-bit up counter                  : 1# Registers                        : 2 1-bit register                    : 2==================================================================================================================================================*                         Low Level Synthesis                           *=========================================================================Optimizing unit <bps> ...Loading device for application Xst from file '2v2000.nph' in environment C:/Xilinx.Mapping all equations...Building and optimizing final netlist ...Found area constraint ratio of 100 (+ 5) on block bps, actual ratio is 0.=========================================================================*                            Final Report                               *=========================================================================Device utilization summary:---------------------------Selected Device : 2v2000bf957-4  Number of Slices:                       8  out of  10752     0%   Number of Slice Flip Flops:            10  out of  21504     0%   Number of 4 input LUTs:                 9  out of  21504     0%   Number of bonded IOBs:                  3  out of    624     0%  =========================================================================TIMING REPORTClock Information:-----------------------------------------------------+------------------------+-------+Clock Signal                       | Clock buffer(FF name)  | Load  |-----------------------------------+------------------------+-------+clk                                | IBUF                   | 10    |-----------------------------------+------------------------+-------+Timing Summary:---------------Speed Grade: -4   Minimum period: 5.231ns (Maximum Frequency: 191.168MHz)   Minimum input arrival time before clock: 2.723ns   Maximum output required time after clock: 5.446ns   Maximum combinational path delay: No path found=========================================================================Completed process "Synthesize".

Project Navigator Auto-Make Log File-------------------------------------



Started process "Synthesize".=========================================================================*                          HDL Compilation                              *=========================================================================Compiling vhdl file E:/aa/bps.vhdl in Library work.Entity <bps> (Architecture <main>) compiled.=========================================================================*                            HDL Analysis                               *=========================================================================Analyzing Entity <bps> (Architecture <main>).Entity <bps> analyzed. Unit <bps> generated.=========================================================================*                           HDL Synthesis                               *=========================================================================Synthesizing Unit <bps>.    Related source file is E:/aa/bps.vhdl.    Found 1-bit register for signal <clktr>.    Found 8-bit up counter for signal <count>.    Found 1-bit register for signal <temp>.    Summary:	inferred   1 Counter(s).	inferred   2 D-type flip-flop(s).Unit <bps> synthesized.=========================================================================*                       Advanced HDL Synthesis                          *=========================================================================Advanced RAM inference ...Advanced multiplier inference ...Dynamic shift register inference ...=========================================================================HDL Synthesis ReportMacro Statistics# Counters                         : 1 8-bit up counter                  : 1# Registers                        : 2 1-bit register                    : 2==================================================================================================================================================*                         Low Level Synthesis                           *=========================================================================Optimizing unit <bps> ...Loading device for application Xst from file '2v2000.nph' in environment C:/Xilinx.Mapping all equations...Building and optimizing final netlist ...Found area constraint ratio of 100 (+ 5) on block bps, actual ratio is 0.=========================================================================*                            Final Report                               *=========================================================================Device utilization summary:---------------------------Selected Device : 2v2000bf957-4  Number of Slices:                       8  out of  10752     0%   Number of Slice Flip Flops:            10  out of  21504     0%   Number of 4 input LUTs:                 9  out of  21504     0%   Number of bonded IOBs:                  3  out of    624     0%  =========================================================================TIMING REPORTClock Information:-----------------------------------------------------+------------------------+-------+Clock Signal                       | Clock buffer(FF name)  | Load  |-----------------------------------+------------------------+-------+clk                                | IBUF                   | 10    |-----------------------------------+------------------------+--
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