__projnav.log

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Entity <xmit> (Architecture <main>) compiled.


Project Navigator Auto-Make Log File-------------------------------------



Started process "Synthesize".=========================================================================*                          HDL Compilation                              *=========================================================================Compiling vhdl file D:/aa/bps.vhdl in Library work.ERROR:HDLParsers:164 - D:/aa/bps.vhdl Line 24. parse error, unexpected ELSIF, expecting SEMICOLON--> Total memory usage is 63740 kilobytesERROR: XST failedProcess "Synthesize" did not complete.
Project Navigator Auto-Make Log File-------------------------------------



Started process "Synthesize".=========================================================================*                          HDL Compilation                              *=========================================================================Compiling vhdl file D:/aa/bps.vhdl in Library work.ERROR:HDLParsers:164 - D:/aa/bps.vhdl Line 24. parse error, unexpected ELSIF, expecting SEMICOLON--> Total memory usage is 63740 kilobytesERROR: XST failedProcess "Synthesize" did not complete.
Project Navigator Auto-Make Log File-------------------------------------



Started process "Synthesize".=========================================================================*                          HDL Compilation                              *=========================================================================Compiling vhdl file D:/aa/bps.vhdl in Library work.ERROR:HDLParsers:164 - D:/aa/bps.vhdl Line 24. parse error, unexpected ELSIF, expecting SEMICOLONERROR:HDLParsers:164 - D:/aa/bps.vhdl Line 32. parse error, unexpected IF, expecting PROCESS--> Total memory usage is 63740 kilobytesERROR: XST failedProcess "Synthesize" did not complete.
Project Navigator Auto-Make Log File-------------------------------------



Started process "Synthesize".=========================================================================*                          HDL Compilation                              *=========================================================================Compiling vhdl file D:/aa/bps.vhdl in Library work.ERROR:HDLParsers:164 - D:/aa/bps.vhdl Line 24. parse error, unexpected ELSIF, expecting SEMICOLONERROR:HDLParsers:164 - D:/aa/bps.vhdl Line 33. parse error, unexpected IF, expecting PROCESS--> Total memory usage is 63740 kilobytesERROR: XST failedProcess "Synthesize" did not complete.
Project Navigator Auto-Make Log File-------------------------------------



Started process "Synthesize".=========================================================================*                          HDL Compilation                              *=========================================================================Compiling vhdl file D:/aa/bps.vhdl in Library work.ERROR:HDLParsers:164 - D:/aa/bps.vhdl Line 24. parse error, unexpected ELSIF, expecting SEMICOLONERROR:HDLParsers:164 - D:/aa/bps.vhdl Line 32. parse error, unexpected IF, expecting PROCESS--> Total memory usage is 63740 kilobytesERROR: XST failedProcess "Synthesize" did not complete.
Project Navigator Auto-Make Log File-------------------------------------



Started process "Synthesize".=========================================================================*                          HDL Compilation                              *=========================================================================Compiling vhdl file D:/aa/bps.vhdl in Library work.ERROR:HDLParsers:164 - D:/aa/bps.vhdl Line 24. parse error, unexpected ELSIF, expecting SEMICOLONERROR:HDLParsers:164 - D:/aa/bps.vhdl Line 33. parse error, unexpected IF, expecting PROCESS--> Total memory usage is 63740 kilobytesERROR: XST failedProcess "Synthesize" did not complete.
Project Navigator Auto-Make Log File-------------------------------------



Started process "Synthesize".=========================================================================*                          HDL Compilation                              *=========================================================================Compiling vhdl file D:/aa/bps.vhdl in Library work.Entity <bps> (Architecture <main>) compiled.=========================================================================*                            HDL Analysis                               *=========================================================================Analyzing Entity <bps> (Architecture <main>).INFO:Xst:1739 - HDL ADVISOR - D:/aa/bps.vhdl line 14: declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output.Entity <bps> analyzed. Unit <bps> generated.=========================================================================*                           HDL Synthesis                               *=========================================================================Synthesizing Unit <bps>.    Related source file is D:/aa/bps.vhdl.    Found 1-bit register for signal <clktr>.    Found 8-bit up counter for signal <count>.    Summary:	inferred   1 Counter(s).	inferred   1 D-type flip-flop(s).Unit <bps> synthesized.=========================================================================*                       Advanced HDL Synthesis                          *=========================================================================Advanced RAM inference ...Advanced multiplier inference ...Dynamic shift register inference ...=========================================================================HDL Synthesis ReportMacro Statistics# Counters                         : 1 8-bit up counter                  : 1# Registers                        : 1 1-bit register                    : 1==================================================================================================================================================*                         Low Level Synthesis                           *=========================================================================Optimizing unit <bps> ...Loading device for application Xst from file '2v2000.nph' in environment D:/Xilinx.Mapping all equations...Building and optimizing final netlist ...Found area constraint ratio of 100 (+ 5) on block bps, actual ratio is 0.=========================================================================*                            Final Report                               *=========================================================================Device utilization summary:---------------------------Selected Device : 2v2000bf957-4  Number of Slices:                       8  out of  10752     0%   Number of Slice Flip Flops:             9  out of  21504     0%   Number of 4 input LUTs:                 9  out of  21504     0%   Number of bonded IOBs:                  3  out of    624     0%  =========================================================================TIMING REPORTClock Information:-----------------------------------------------------+------------------------+-------+Clock Signal                       | Clock buffer(FF name)  | Load  |-----------------------------------+------------------------+-------+clk                                | IBUF                   | 9     |-----------------------------------+------------------------+-------+Timing Summary:---------------Speed Grade: -4   Minimum period: 5.231ns (Maximum Frequency: 191.168MHz)   Minimum input arrival time before clock: 2.723ns   Maximum output required time after clock: 5.630ns   Maximum combinational path delay: No path found=========================================================================Completed process "Synthesize".

Project Navigator Auto-Make Log File-------------------------------------



Started process "Synthesize".=========================================================================*                          HDL Compilation                              *=========================================================================WARNING:HDLParsers:3215 - Unit work/BPS is now defined in a different file: was D:/aa/bps.vhdl, now is E:/aa/bps.vhdlWARNING:HDLParsers:3215 - Unit work/BPS/MAIN is now defined in a different file: was D:/aa/bps.vhdl, now is E:/aa/bps.vhdlCompiling vhdl file E:/aa/bps.vhdl in Library work.Entity <bps> (Architecture <main>) compiled.=========================================================================*                            HDL Analysis                               *=========================================================================Analyzing Entity <bps> (Architecture <main>).INFO:Xst:1739 - HDL ADVISOR - E:/aa/bps.vhdl line 14: declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output.Entity <bps> analyzed. Unit <bps> generated.=========================================================================*                           HDL Synthesis                               *=========================================================================Synthesizing Unit <bps>.    Related source file is E:/aa/bps.vhdl.    Found 1-bit register for signal <clktr>.    Found 8-bit up counter for signal <count>.    Summary:	inferred   1 Counter(s).	inferred   1 D-type flip-flop(s).Unit <bps> synthesized.=========================================================================*                       Advanced HDL Synthesis                          *=========================================================================Advanced RAM inference ...Advanced multiplier inference ...Dynamic shift register inference ...=========================================================================HDL Synthesis ReportMacro Statistics# Counters                         : 1 8-bit up counter                  : 1# Registers                        : 1 1-bit register                    : 1==================================================================================================================================================*                         Low Level Synthesis                           *=========================================================================Optimizing unit <bps> ...Loading device for application Xst from file '2v2000.nph' in environment C:/Xilinx.Mapping all equations...Building and optimizing final netlist ...Found area constraint ratio of 100 (+ 5) on block bps, actual ratio is 0.=========================================================================*                            Final Report                               *=========================================================================Device utilization summary:---------------------------Selected Device : 2v2000bf957-4  Number of Slices:                       8  out of  10752     0%   Number of Slice Flip Flops:             9  out of  21504     0%   Number of 4 input LUTs:                 9  out of  21504     0%   Number of bonded IOBs:                  3  out of    624     0%  =========================================================================TIMING REPORTClock Information:-----------------------------------------------------+------------------------+-------+Clock Signal                       | Clock buffer(FF name)  | Load  |-----------------------------------+------------------------+-------+clk                                | IBUF                   | 9     |-----------------------------------+------------------------+-------+Timing Summary:---------------Speed Grade: -4   Minimum period: 5.231ns (Maximum Frequency: 191.168MHz)   Minimum input arrival time before clock: 2.723ns   Maximum output required time after clock: 5.630ns
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