__projnav.log
来自「xilinx环境下开发vhdl语言串行接口设计」· LOG 代码 · 共 1,782 行 · 第 1/5 页
LOG
1,782 行
WARNING:Xst:737 - Found 1-bit latch for signal <rdata_5>.WARNING:Xst:737 - Found 1-bit latch for signal <rdata_4>.WARNING:Xst:737 - Found 1-bit latch for signal <rdata_3>.WARNING:Xst:737 - Found 1-bit latch for signal <rdata_2>.WARNING:Xst:737 - Found 1-bit latch for signal <rdata_1>.WARNING:Xst:737 - Found 1-bit latch for signal <rdata_0>.WARNING:Xst:737 - Found 1-bit latch for signal <rcving>.WARNING:Xst:737 - Found 1-bit latch for signal <done_rcving>. Found 1-bit register for signal <enclk>. Found 4-bit up counter for signal <count>. Summary: inferred 1 Counter(s). inferred 1 D-type flip-flop(s).Unit <rev> synthesized.=========================================================================* Advanced HDL Synthesis *=========================================================================Advanced RAM inference ...Advanced multiplier inference ...Dynamic shift register inference ...=========================================================================HDL Synthesis ReportMacro Statistics# Counters : 1 4-bit up counter : 1# Registers : 1 1-bit register : 1# Latches : 10 1-bit latch : 10==================================================================================================================================================* Low Level Synthesis *=========================================================================Optimizing unit <rev> ...Loading device for application Xst from file '2v2000.nph' in environment C:/Xilinx.Mapping all equations...Building and optimizing final netlist ...Found area constraint ratio of 100 (+ 5) on block rev, actual ratio is 0.=========================================================================* Final Report *=========================================================================Device utilization summary:---------------------------Selected Device : 2v2000bf957-4 Number of Slices: 12 out of 10752 0% Number of Slice Flip Flops: 15 out of 21504 0% Number of 4 input LUTs: 19 out of 21504 0% Number of bonded IOBs: 14 out of 624 2% =========================================================================TIMING REPORTClock Information:-----------------------------------------------------+------------------------+-------+Clock Signal | Clock buffer(FF name) | Load |-----------------------------------+------------------------+-------+_n0056(_n00561:O) | NONE(*)(done_rcving) | 1 |_n0055(_n00551:O) | NONE(*)(rcving) | 1 |_n0012(_n00121:O) | NONE(*)(rdata_7) | 1 |_n0014(_n00141:O) | NONE(*)(rdata_5) | 1 |_n0019(_n00191:O) | NONE(*)(rdata_0) | 1 |clktr | IBUF | 4 |_n0018(_n00181:O) | NONE(*)(rdata_1) | 1 |_n0017(_n00171:O) | NONE(*)(rdata_2) | 1 |_n0016(_n00161:O) | NONE(*)(rdata_3) | 1 |_n0013(_n00131:O) | NONE(*)(rdata_6) | 1 |_n0015(_n00151:O) | NONE(*)(rdata_4) | 1 |startm(startm1:O) | NONE(*)(enclk) | 1 |-----------------------------------+------------------------+-------+(*) These 11 clock signal(s) are generated by combinatorial logic,and XST is not able to identify which are the primary clock signals.Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic.Timing Summary:---------------Speed Grade: -4 Minimum period: 2.378ns (Maximum Frequency: 420.610MHz) Minimum input arrival time before clock: 2.427ns Maximum output required time after clock: 5.552ns Maximum combinational path delay: No path found=========================================================================Completed process "Synthesize".
Project Navigator Auto-Make Log File-------------------------------------
Compiling vhdl file D:/WorkSpace/Xilinx/dl/aa/rev.vhdl in Library work.Entity <rev> (Architecture <main>) compiled.
Project Navigator Auto-Make Log File-------------------------------------
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling vhdl file D:/WorkSpace/Xilinx/dl/aa/xmit.vhdl in Library work.Entity <xmit> (Architecture <main>) compiled.=========================================================================* HDL Analysis *=========================================================================Analyzing Entity <xmit> (Architecture <main>).WARNING:Xst:819 - D:/WorkSpace/Xilinx/dl/aa/xmit.vhdl line 45: The following signals are missing in the process sensitivity list: tdata.Entity <xmit> analyzed. Unit <xmit> generated.=========================================================================* HDL Synthesis *=========================================================================Synthesizing Unit <xmit>. Related source file is D:/WorkSpace/Xilinx/dl/aa/xmit.vhdl.WARNING:Xst:737 - Found 1-bit latch for signal <txd>.WARNING:Xst:737 - Found 1-bit latch for signal <xmitting>.WARNING:Xst:737 - Found 1-bit latch for signal <done_xmitting>. Found 4-bit up counter for signal <count>. Summary: inferred 1 Counter(s).Unit <xmit> synthesized.=========================================================================* Advanced HDL Synthesis *=========================================================================Advanced RAM inference ...Advanced multiplier inference ...Dynamic shift register inference ...=========================================================================HDL Synthesis ReportMacro Statistics# Counters : 1 4-bit up counter : 1# Latches : 3 1-bit latch : 3==================================================================================================================================================* Low Level Synthesis *=========================================================================Optimizing unit <xmit> ...Loading device for application Xst from file '2v2000.nph' in environment C:/Xilinx.Mapping all equations...Building and optimizing final netlist ...Found area constraint ratio of 100 (+ 5) on block xmit, actual ratio is 0.=========================================================================* Final Report *=========================================================================Device utilization summary:---------------------------Selected Device : 2v2000bf957-4 Number of Slices: 13 out of 10752 0% Number of Slice Flip Flops: 7 out of 21504 0% Number of 4 input LUTs: 22 out of 21504 0% Number of bonded IOBs: 14 out of 624 2% =========================================================================TIMING REPORTClock Information:-----------------------------------------------------+------------------------+-------+Clock Signal | Clock buffer(FF name) | Load |-----------------------------------+------------------------+-------+clrn | IBUF | 1 |_n0027(_n0027:O) | NONE(*)(xmitting) | 2 |clktr | IBUF | 4 |-----------------------------------+------------------------+-------+(*) This 1 clock signal(s) are generated by combinatorial logic,and XST is not able to identify which are the primary clock signals.Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic.Timing Summary:---------------Speed Grade: -4 Minimum period: 2.355ns (Maximum Frequency: 424.719MHz) Minimum input arrival time before clock: 5.021ns Maximum output required time after clock: 5.736ns Maximum combinational path delay: 5.979ns=========================================================================Completed process "Synthesize".
Project Navigator Auto-Make Log File-------------------------------------
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling vhdl file D:/WorkSpace/Xilinx/dl/aa/xmit.vhdl in Library work.Entity <xmit> (Architecture <main>) compiled.=========================================================================* HDL Analysis *=========================================================================Analyzing Entity <xmit> (Architecture <main>).WARNING:Xst:819 - D:/WorkSpace/Xilinx/dl/aa/xmit.vhdl line 45: The following signals are missing in the process sensitivity list: tdata.Entity <xmit> analyzed. Unit <xmit> generated.=========================================================================* HDL Synthesis *=========================================================================Synthesizing Unit <xmit>. Related source file is D:/WorkSpace/Xilinx/dl/aa/xmit.vhdl.WARNING:Xst:737 - Found 1-bit latch for signal <txd>.WARNING:Xst:737 - Found 1-bit latch for signal <xmitting>.WARNING:Xst:737 - Found 1-bit latch for signal <done_xmitting>. Found 4-bit up counter for signal <count>. Summary: inferred 1 Counter(s).Unit <xmit> synthesized.=========================================================================* Advanced HDL Synthesis *=========================================================================Advanced RAM inference ...Advanced multiplier inference ...Dynamic shift register inference ...=========================================================================HDL Synthesis ReportMacro Statistics# Counters : 1 4-bit up counter : 1# Latches : 3 1-bit latch : 3==================================================================================================================================================* Low Level Synthesis *=========================================================================Optimizing unit <xmit> ...Loading device for application Xst from file '2v2000.nph' in environment C:/Xilinx.Mapping all equations...Building and optimizing final netlist ...Found area constraint ratio of 100 (+ 5) on block xmit, actual ratio is 0.=========================================================================* Final Report *=========================================================================Device utilization summary:---------------------------Selected Device : 2v2000bf957-4 Number of Slices: 14 out of 10752 0% Number of Slice Flip Flops: 7 out of 21504 0% Number of 4 input LUTs: 24 out of 21504 0% Number of bonded IOBs: 14 out of 624 2% =========================================================================TIMING REPORTClock Information:-----------------------------------------------------+------------------------+-------+Clock Signal | Clock buffer(FF name) | Load |-----------------------------------+------------------------+-------+clrn | IBUF | 1 |_n0046(_n0046_SW129:O) | NONE(*)(done_xmitting) | 1 |_n0045(_n0045:O) | NONE(*)(xmitting) | 1 |clktr | IBUF | 4 |-----------------------------------+------------------------+-------+(*) These 2 clock signal(s) are generated by combinatorial logic,and XST is not able to identify which are the primary clock signals.Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic.Timing Summary:---------------Speed Grade: -4 Minimum period: 3.164ns (Maximum Frequency: 316.056MHz) Minimum input arrival time before clock: 4.603ns Maximum output required time after clock: 5.760ns Maximum combinational path delay: 6.003ns=========================================================================Completed process "Synthesize".
Project Navigator Auto-Make Log File-------------------------------------
Compiling vhdl file D:/WorkSpace/Xilinx/dl/aa/xmit.vhdl in Library work.⌨️ 快捷键说明
复制代码Ctrl + C
搜索代码Ctrl + F
全屏模式F11
增大字号Ctrl + =
减小字号Ctrl + -
显示快捷键?