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ERROR:HDLParsers:164 - D:\WorkSpace\Xilinx\dl\aa/rev.vhdl Line 48. parse error, unexpected TICK
ERROR:HDLParsers:164 - D:\WorkSpace\Xilinx\dl\aa/rev.vhdl Line 65. parse error, unexpected CASE
ERROR:HDLParsers:164 - D:\WorkSpace\Xilinx\dl\aa/rev.vhdl Line 68. parse error, unexpected WHEN, expecting END
ERROR:HDLParsers:164 - D:\WorkSpace\Xilinx\dl\aa/rev.vhdl Line 76. parse error, unexpected CASE, expecting IF
--> 

Total memory usage is 49124 kilobytes


ERROR: XST failed
Process "Synthesize" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file D:/WorkSpace/Xilinx/dl/aa/rev.vhdl in Library work.
Entity <rev> (Architecture <main>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <rev> (Architecture <main>).
WARNING:Xst:819 - D:/WorkSpace/Xilinx/dl/aa/rev.vhdl line 58: The following signals are missing in the process sensitivity list:
   rxd.
INFO:Xst:1304 - Contents of register <startm> in unit <rev> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <enclk> in unit <rev> never changes during circuit operation. The register is replaced by logic.
Entity <rev> analyzed. Unit <rev> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <rev>.
    Related source file is D:/WorkSpace/Xilinx/dl/aa/rev.vhdl.
WARNING:Xst:646 - Signal <startm> is assigned but never used.
WARNING:Xst:737 - Found 1-bit latch for signal <rdata_7>.
WARNING:Xst:737 - Found 1-bit latch for signal <rdata_6>.
WARNING:Xst:737 - Found 1-bit latch for signal <rdata_5>.
WARNING:Xst:737 - Found 1-bit latch for signal <rdata_4>.
WARNING:Xst:737 - Found 1-bit latch for signal <rdata_3>.
WARNING:Xst:737 - Found 1-bit latch for signal <rdata_2>.
WARNING:Xst:737 - Found 1-bit latch for signal <rdata_1>.
WARNING:Xst:737 - Found 1-bit latch for signal <rdata_0>.
WARNING:Xst:737 - Found 1-bit latch for signal <rcving>.
WARNING:Xst:737 - Found 1-bit latch for signal <done_rcving>.
    Found 4-bit up counter for signal <count>.
    Summary:
	inferred   1 Counter(s).
Unit <rev> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Counters                         : 1
 4-bit up counter                  : 1
# Latches                          : 10
 1-bit latch                       : 10

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <rev> ...
Loading device for application Xst from file '2v2000.nph' in environment C:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block rev, actual ratio is 0.

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2v2000bf957-4 

 Number of Slices:                      10  out of  10752     0%  
 Number of Slice Flip Flops:            14  out of  21504     0%  
 Number of 4 input LUTs:                18  out of  21504     0%  
 Number of bonded IOBs:                 14  out of    624     2%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
_n0055(_n00551:O)                  | NONE(*)(done_rcving)   | 1     |
_n0054(_n00541:O)                  | NONE(*)(rcving)        | 1     |
_n0014(_n00141:O)                  | NONE(*)(rdata_5)       | 1     |
clktr                              | IBUF                   | 4     |
_n0013(_n00131:O)                  | NONE(*)(rdata_6)       | 1     |
_n0019(_n00191:O)                  | NONE(*)(rdata_0)       | 1     |
_n0018(_n00181:O)                  | NONE(*)(rdata_1)       | 1     |
_n0017(_n00171:O)                  | NONE(*)(rdata_2)       | 1     |
_n0016(_n00161:O)                  | NONE(*)(rdata_3)       | 1     |
_n0012(_n00121:O)                  | NONE(*)(rdata_7)       | 1     |
_n0015(_n00151:O)                  | NONE(*)(rdata_4)       | 1     |
-----------------------------------+------------------------+-------+
(*) These 10 clock signal(s) are generated by combinatorial logic,
and XST is not able to identify which are the primary clock signals.
Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic.

Timing Summary:
---------------
Speed Grade: -4

   Minimum period: 2.378ns (Maximum Frequency: 420.610MHz)
   Minimum input arrival time before clock: 2.405ns
   Maximum output required time after clock: 5.552ns
   Maximum combinational path delay: No path found

=========================================================================
Completed process "Synthesize".



Project Navigator Auto-Make Log File
-------------------------------------



Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file D:/WorkSpace/Xilinx/dl/aa/rev.vhdl in Library work.
Entity <rev> (Architecture <main>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <rev> (Architecture <main>).
WARNING:Xst:819 - D:/WorkSpace/Xilinx/dl/aa/rev.vhdl line 59: The following signals are missing in the process sensitivity list:
   rxd.
INFO:Xst:1304 - Contents of register <startm> in unit <rev> never changes during circuit operation. The register is replaced by logic.
Entity <rev> analyzed. Unit <rev> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <rev>.
    Related source file is D:/WorkSpace/Xilinx/dl/aa/rev.vhdl.
WARNING:Xst:737 - Found 1-bit latch for signal <rdata_7>.
WARNING:Xst:737 - Found 1-bit latch for signal <rdata_6>.
WARNING:Xst:737 - Found 1-bit latch for signal <rdata_5>.
WARNING:Xst:737 - Found 1-bit latch for signal <rdata_4>.
WARNING:Xst:737 - Found 1-bit latch for signal <rdata_3>.
WARNING:Xst:737 - Found 1-bit latch for signal <rdata_2>.
WARNING:Xst:737 - Found 1-bit latch for signal <rdata_1>.
WARNING:Xst:737 - Found 1-bit latch for signal <rdata_0>.
WARNING:Xst:737 - Found 1-bit latch for signal <rcving>.
WARNING:Xst:737 - Found 1-bit latch for signal <done_rcving>.
    Found 1-bit register for signal <enclk>.
    Found 4-bit up counter for signal <count>.
    Summary:
	inferred   1 Counter(s).
	inferred   1 D-type flip-flop(s).
Unit <rev> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Counters                         : 1
 4-bit up counter                  : 1
# Registers                        : 1
 1-bit register                    : 1
# Latches                          : 10
 1-bit latch                       : 10

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
WARNING:Xst:528 - Multi-source in Unit <rev> on signal <startm> not replaced by logic
Signal is stuck at GND
ERROR:Xst:415 - Synthesis failed
CPU : 1.44 / 2.02 s | Elapsed : 1.00 / 2.00 s
 
--> 

Total memory usage is 56292 kilobytes


ERROR: XST failed
Process "Synthesize" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file D:/WorkSpace/Xilinx/dl/aa/rev.vhdl in Library work.
Entity <rev> (Architecture <main>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <rev> (Architecture <main>).
WARNING:Xst:819 - D:/WorkSpace/Xilinx/dl/aa/rev.vhdl line 59: The following signals are missing in the process sensitivity list:
   rxd.
INFO:Xst:1304 - Contents of register <startm> in unit <rev> never changes during circuit operation. The register is replaced by logic.
Entity <rev> analyzed. Unit <rev> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <rev>.
    Related source file is D:/WorkSpace/Xilinx/dl/aa/rev.vhdl.
WARNING:Xst:737 - Found 1-bit latch for signal <rdata_7>.
WARNING:Xst:737 - Found 1-bit latch for signal <rdata_6>.
WARNING:Xst:737 - Found 1-bit latch for signal <rdata_5>.
WARNING:Xst:737 - Found 1-bit latch for signal <rdata_4>.
WARNING:Xst:737 - Found 1-bit latch for signal <rdata_3>.
WARNING:Xst:737 - Found 1-bit latch for signal <rdata_2>.
WARNING:Xst:737 - Found 1-bit latch for signal <rdata_1>.
WARNING:Xst:737 - Found 1-bit latch for signal <rdata_0>.
WARNING:Xst:737 - Found 1-bit latch for signal <rcving>.
WARNING:Xst:737 - Found 1-bit latch for signal <done_rcving>.
    Found 1-bit register for signal <enclk>.
    Found 4-bit up counter for signal <count>.
    Summary:
	inferred   1 Counter(s).
	inferred   1 D-type flip-flop(s).
Unit <rev> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Counters                         : 1
 4-bit up counter                  : 1
# Registers                        : 1
 1-bit register                    : 1
# Latches                          : 10
 1-bit latch                       : 10

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
WARNING:Xst:528 - Multi-source in Unit <rev> on signal <startm> not replaced by logic
Signal is stuck at GND
ERROR:Xst:415 - Synthesis failed
CPU : 1.42 / 2.00 s | Elapsed : 2.00 / 2.00 s
 
--> 

Total memory usage is 56228 kilobytes


ERROR: XST failed
Process "Synthesize" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file D:/WorkSpace/Xilinx/dl/aa/rev.vhdl in Library work.
Entity <rev> (Architecture <main>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <rev> (Architecture <main>).
WARNING:Xst:819 - D:/WorkSpace/Xilinx/dl/aa/rev.vhdl line 58: The following signals are missing in the process sensitivity list:
   rxd.
Entity <rev> analyzed. Unit <rev> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <rev>.
    Related source file is D:/WorkSpace/Xilinx/dl/aa/rev.vhdl.
WARNING:Xst:737 - Found 1-bit latch for signal <rdata_7>.
WARNING:Xst:737 - Found 1-bit latch for signal <rdata_6>.