__projnav.log
来自「xilinx环境下开发vhdl语言串行接口设计」· LOG 代码 · 共 1,782 行 · 第 1/5 页
LOG
1,782 行
Project Navigator Auto-Make Log File-------------------------------------
Project Navigator Auto-Make Log File-------------------------------------
Project Navigator Auto-Make Log File-------------------------------------
Project Navigator Auto-Make Log File-------------------------------------
Project Navigator Auto-Make Log File-------------------------------------
Compiling vhdl file d:/xilinxise6.2/aa/rev.vhdl in Library work.ERROR:HDLParsers:3345 - d:/xilinxise6.2/aa/rev.vhdl Line 23. Only SHARED variables can be declared here.ERROR:HDLParsers:164 - d:/xilinxise6.2/aa/rev.vhdl Line 41. parse error, unexpected EQ, expecting OPENPAR or TICK or LSQBRACKERROR:HDLParsers:164 - d:/xilinxise6.2/aa/rev.vhdl Line 46. parse error, unexpected PLUS, expecting OPENPAR or TICK or LSQBRACKERROR:HDLParsers:808 - d:/xilinxise6.2/aa/rev.vhdl Line 48. = can not have such operands in this context.
Launching Application for process "Generate Expected Simulation Results".Reading D:/Modeltech_xe/tcl/vsim/pref.tcl # 5.6a# do test2.ado listening on address 127.0.0.1 port 1200# ** Warning: (vlib-34) Library already exists at "work".# resume# Model Technology ModelSim XE vcom 5.6a Compiler 2002.04 Apr 29 2002# -- Loading package standard# -- Loading package std_logic_1164# -- Loading package std_logic_arith# -- Loading package std_logic_unsigned# -- Compiling entity rev# -- Compiling architecture main of rev# ERROR: rev.vhdl(41): near "=": expecting: <= :=# ERROR: rev.vhdl(46): near "+": expecting: <= :=# ERROR: rev.vhdl(47): near ";": expecting: GENERATE THEN# ERROR: rev.vhdl(52): near "if": expecting: PROCESS# ERROR: invalid command name "bind"# Initialization problem, exiting.# Executing ONERROR command at macro ./test2.ado line 10ERROR: VSim failed to simulate annotated testbench
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling vhdl file d:/xilinxise6.2/aa/rev.vhdl in Library work.ERROR:HDLParsers:3345 - d:/xilinxise6.2/aa/rev.vhdl Line 23. Only SHARED variables can be declared here.ERROR:HDLParsers:164 - d:/xilinxise6.2/aa/rev.vhdl Line 41. parse error, unexpected EQ, expecting OPENPAR or TICK or LSQBRACKERROR:HDLParsers:164 - d:/xilinxise6.2/aa/rev.vhdl Line 46. parse error, unexpected PLUS, expecting OPENPAR or TICK or LSQBRACKERROR:HDLParsers:808 - d:/xilinxise6.2/aa/rev.vhdl Line 48. = can not have such operands in this context.--> Total memory usage is 48264 kilobytesERROR: XST failedProcess "Synthesize" did not complete.
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling vhdl file d:/xilinxise6.2/aa/rev.vhdl in Library work.ERROR:HDLParsers:3345 - d:/xilinxise6.2/aa/rev.vhdl Line 23. Only SHARED variables can be declared here.ERROR:HDLParsers:164 - d:/xilinxise6.2/aa/rev.vhdl Line 41. parse error, unexpected AFFECT, expecting OPENPAR or TICK or LSQBRACKERROR:HDLParsers:808 - d:/xilinxise6.2/aa/rev.vhdl Line 48. = can not have such operands in this context.--> Total memory usage is 48264 kilobytesERROR: XST failedProcess "Synthesize" did not complete.
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling vhdl file d:/xilinxise6.2/aa/rev.vhdl in Library work.ERROR:HDLParsers:3345 - d:/xilinxise6.2/aa/rev.vhdl Line 23. Only SHARED variables can be declared here.ERROR:HDLParsers:164 - d:/xilinxise6.2/aa/rev.vhdl Line 41. parse error, unexpected AFFECT, expecting OPENPAR or TICK or LSQBRACKERROR:HDLParsers:808 - d:/xilinxise6.2/aa/rev.vhdl Line 48. = can not have such operands in this context.--> Total memory usage is 48264 kilobytesERROR: XST failedProcess "Synthesize" did not complete.
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling vhdl file d:/xilinxise6.2/aa/rev.vhdl in Library work.ERROR:HDLParsers:3345 - d:/xilinxise6.2/aa/rev.vhdl Line 23. Only SHARED variables can be declared here.ERROR:HDLParsers:800 - d:/xilinxise6.2/aa/rev.vhdl Line 44. Type of i is incompatible with type of '0'.ERROR:HDLParsers:808 - d:/xilinxise6.2/aa/rev.vhdl Line 49. = can not have such operands in this context.--> Total memory usage is 48264 kilobytesERROR: XST failedProcess "Synthesize" did not complete.
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling vhdl file d:/xilinxise6.2/aa/rev.vhdl in Library work.ERROR:HDLParsers:800 - d:/xilinxise6.2/aa/rev.vhdl Line 44. Type of i is incompatible with type of '0'.ERROR:HDLParsers:808 - d:/xilinxise6.2/aa/rev.vhdl Line 49. = can not have such operands in this context.--> Total memory usage is 48264 kilobytesERROR: XST failedProcess "Synthesize" did not complete.
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling vhdl file d:/xilinxise6.2/aa/rev.vhdl in Library work.ERROR:HDLParsers:808 - d:/xilinxise6.2/aa/rev.vhdl Line 49. = can not have such operands in this context.--> Total memory usage is 48264 kilobytesERROR: XST failedProcess "Synthesize" did not complete.
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling vhdl file d:/xilinxise6.2/aa/rev.vhdl in Library work.ERROR:HDLParsers:164 - d:/xilinxise6.2/aa/rev.vhdl Line 49. parse error, unexpected AFFECT, expecting THENERROR:HDLParsers:164 - d:/xilinxise6.2/aa/rev.vhdl Line 53. parse error, unexpected IF, expecting PROCESS--> Total memory usage is 48264 kilobytesERROR: XST failedProcess "Synthesize" did not complete.
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================WARNING:HDLParsers:3215 - Unit work/REV is now defined in a different file: was d:/xilinxise6.2/aa/rev.vhdl, now is D:/WorkSpace/Xilinx/dl/aa/rev.vhdlWARNING:HDLParsers:3215 - Unit work/REV/MAIN is now defined in a different file: was d:/xilinxise6.2/aa/rev.vhdl, now is D:/WorkSpace/Xilinx/dl/aa/rev.vhdlCompiling vhdl file D:/WorkSpace/Xilinx/dl/aa/rev.vhdl in Library work.Entity <rev> (Architecture <main>) compiled.=========================================================================* HDL Analysis *=========================================================================Analyzing Entity <rev> (Architecture <main>).INFO:Xst:1304 - Contents of register <startm> in unit <rev> never changes during circuit operation. The register is replaced by logic.INFO:Xst:1304 - Contents of register <enclk> in unit <rev> never changes during circuit operation. The register is replaced by logic.INFO:Xst:1304 - Contents of register <start> in unit <rev> never changes during circuit operation. The register is replaced by logic.INFO:Xst:1304 - Contents of register <rcving> in unit <rev> never changes during circuit operation. The register is replaced by logic.Entity <rev> analyzed. Unit <rev> generated.=========================================================================* HDL Synthesis *=========================================================================Synthesizing Unit <rev>. Related source file is D:/WorkSpace/Xilinx/dl/aa/rev.vhdl.WARNING:Xst:1306 - Output <done_rcving> is never assigned.WARNING:Xst:1306 - Output <rdata<7:1>> is never assigned.WARNING:Xst:646 - Signal <startm> is assigned but never used. Found 1-bit register for signal <rdata<0>>. Summary: inferred 1 D-type flip-flop(s).Unit <rev> synthesized.=========================================================================* Advanced HDL Synthesis *=========================================================================Advanced RAM inference ...Advanced multiplier inference ...Dynamic shift register inference ...=========================================================================HDL Synthesis ReportMacro Statistics# Registers : 1 1-bit register : 1==================================================================================================================================================* Low Level Synthesis *=========================================================================Optimizing unit <rev> ...Loading device for application Xst from file '2v2000.nph' in environment C:/Xilinx.Mapping all equations...Building and optimizing final netlist ...Found area constraint ratio of 100 (+ 5) on block rev, actual ratio is 0.=========================================================================* Final Report *=========================================================================Device utilization summary:---------------------------Selected Device : 2v2000bf957-4 Number of Slices: 1 out of 10752 0% Number of Slice Flip Flops: 1 out of 21504 0% Number of bonded IOBs: 5 out of 624 0% =========================================================================TIMING REPORTClock Information:-----------------------------------------------------+------------------------+-------+Clock Signal | Clock buffer(FF name) | Load |-----------------------------------+------------------------+-------+clktr | IBUF | 1 |-----------------------------------+------------------------+-------+Timing Summary:---------------Speed Grade: -4 Minimum period: No path found Minimum input arrival time before clock: 1.712ns Maximum output required time after clock: 5.446ns Maximum combinational path delay: No path found=========================================================================Completed process "Synthesize".
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================WARNING:HDLParsers:3458 - Because of erroneous VHDL in VHDL file D:\WorkSpace\Xilinx\dl\aa/rev.vhdl, automatic determination of correct order of compilation of files in project file rev_vhdl.prj is not possible. Please compile your vhdl file(s) individually to find and fix the error(s) in your vhdl file(s). Defaulting to compilation in the order vhdl file names appear in the project file.Compiling vhdl file D:\WorkSpace\Xilinx\dl\aa/rev.vhdl in Library work.⌨️ 快捷键说明
复制代码Ctrl + C
搜索代码Ctrl + F
全屏模式F11
增大字号Ctrl + =
减小字号Ctrl + -
显示快捷键?