test5.ant

来自「xilinx环境下开发vhdl语言串行接口设计」· ANT 代码 · 共 190 行

-- E:\AA
-- VHDL Annotation Test Bench created by
-- HDL Bencher 6.1i
-- Fri Oct 31 15:31:06 2008

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_TEXTIO.ALL;
USE STD.TEXTIO.ALL;

ENTITY test5 IS
END test5;

ARCHITECTURE testbench_arch OF test5 IS
-- If you get a compiler error on the following line,
-- from the menu do Options->Configuration select VHDL 87
FILE RESULTS: TEXT OPEN WRITE_MODE IS "e:\aa\test5.ano";
	COMPONENT ctrl
		PORT (
			rst : In  std_logic;
			npreq : In  std_logic;
			nprd : In  std_logic;
			npwr : In  std_logic;
			ioab : In  std_logic_vector (1 DOWNTO 0);
			iodb : InOut  std_logic_vector (7 DOWNTO 0);
			tdata : Out  std_logic_vector (7 DOWNTO 0);
			rdata : In  std_logic_vector (7 DOWNTO 0);
			rcving : In  std_logic;
			done_rcving : In  std_logic;
			xmitting : In  std_logic;
			done_xmitting : In  std_logic
		);
	END COMPONENT;

	SIGNAL rst : std_logic;
	SIGNAL npreq : std_logic;
	SIGNAL nprd : std_logic;
	SIGNAL npwr : std_logic;
	SIGNAL ioab : std_logic_vector (1 DOWNTO 0);
	SIGNAL iodb : std_logic_vector (7 DOWNTO 0);
	SIGNAL tdata : std_logic_vector (7 DOWNTO 0);
	SIGNAL rdata : std_logic_vector (7 DOWNTO 0);
	SIGNAL rcving : std_logic;
	SIGNAL done_rcving : std_logic;
	SIGNAL xmitting : std_logic;
	SIGNAL done_xmitting : std_logic;

BEGIN
	UUT : ctrl
	PORT MAP (
		rst => rst,
		npreq => npreq,
		nprd => nprd,
		npwr => npwr,
		ioab => ioab,
		iodb => iodb,
		tdata => tdata,
		rdata => rdata,
		rcving => rcving,
		done_rcving => done_rcving,
		xmitting => xmitting,
		done_xmitting => done_xmitting
	);

	PROCESS -- Annotate outputs process
		VARIABLE TX_TIME : INTEGER :=0;

		PROCEDURE ANNOTATE_tdata(
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			STD.TEXTIO.write(TX_LOC,string'("Annotate["));
			STD.TEXTIO.write(TX_LOC, TX_TIME);
			STD.TEXTIO.write(TX_LOC,string'(",tdata,"));
			IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, tdata);
			STD.TEXTIO.write(TX_LOC, string'("]"));
			TX_STR(TX_LOC.all'range) := TX_LOC.all;
			STD.TEXTIO.writeline(results, TX_LOC);
			STD.TEXTIO.Deallocate(TX_LOC);
		END;

		PROCEDURE ANNOTATE_iodb(
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			STD.TEXTIO.write(TX_LOC,string'("Annotate["));
			STD.TEXTIO.write(TX_LOC, TX_TIME);
			STD.TEXTIO.write(TX_LOC,string'(",iodb,"));
			IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, iodb);
			STD.TEXTIO.write(TX_LOC, string'("]"));
			TX_STR(TX_LOC.all'range) := TX_LOC.all;
			STD.TEXTIO.writeline(results, TX_LOC);
			STD.TEXTIO.Deallocate(TX_LOC);
		END;

	BEGIN
		CHECK_LOOP : LOOP
		WAIT FOR 50 ns;
		TX_TIME := TX_TIME + 50;
		ANNOTATE_tdata(TX_TIME);
		ANNOTATE_iodb(TX_TIME);
		WAIT FOR 50 ns;
		TX_TIME := TX_TIME + 50;
		END LOOP CHECK_LOOP;
	END PROCESS;

	PROCESS
		VARIABLE TX_OUT : LINE;

		BEGIN
		-- --------------------
		rst <= transport '0';
		npreq <= transport '0';
		nprd <= transport '0';
		npwr <= transport '0';
		ioab <= transport std_logic_vector'("00"); --0
		rdata <= transport std_logic_vector'("00000000"); --0
		rcving <= transport '0';
		done_rcving <= transport '0';
		xmitting <= transport '0';
		done_xmitting <= transport '0';
		iodb <= transport std_logic_vector'("ZZZZZZZZ"); --Z
		-- --------------------
		WAIT FOR 100 ns; -- Time=100 ns
		rst <= transport '1';
		ioab <= transport std_logic_vector'("00"); --0
		rdata <= transport std_logic_vector'("01001010"); --4A
		done_xmitting <= transport '1';
		iodb <= transport std_logic_vector'("01001011"); --4B
		-- --------------------
		WAIT FOR 100 ns; -- Time=200 ns
		npreq <= transport '1';
		npwr <= transport '1';
		-- --------------------
		WAIT FOR 100 ns; -- Time=300 ns
		ioab <= transport std_logic_vector'("00"); --0
		-- --------------------
		WAIT FOR 100 ns; -- Time=400 ns
		ioab <= transport std_logic_vector'("00"); --0
		rdata <= transport std_logic_vector'("11010010"); --D2
		-- --------------------
		WAIT FOR 100 ns; -- Time=500 ns
		rst <= transport '0';
		npwr <= transport '0';
		ioab <= transport std_logic_vector'("00"); --0
		-- --------------------
		WAIT FOR 100 ns; -- Time=600 ns
		rst <= transport '1';
		nprd <= transport '1';
		ioab <= transport std_logic_vector'("01"); --1
		rcving <= transport '1';
		iodb <= transport std_logic_vector'("ZZZZZZZZ"); --Z
		-- --------------------
		WAIT FOR 100 ns; -- Time=700 ns
		npwr <= transport '0';
		ioab <= transport std_logic_vector'("01"); --1
		rcving <= transport '0';
		xmitting <= transport '1';
		-- --------------------
		WAIT FOR 100 ns; -- Time=800 ns
		npwr <= transport '0';
		rcving <= transport '1';
		done_rcving <= transport '0';
		xmitting <= transport '0';
		-- --------------------
		WAIT FOR 200 ns; -- Time=1000 ns
		npreq <= transport '0';
		-- --------------------
		WAIT FOR 1900 ns; -- Time=2900 ns
		-- --------------------

		STD.TEXTIO.write(TX_OUT, string'("Total[]"));
		STD.TEXTIO.writeline(results, TX_OUT);
		ASSERT (FALSE) REPORT
			"Success! Simulation for annotation completed"
			SEVERITY FAILURE;
	END PROCESS;
END testbench_arch;

CONFIGURATION ctrl_cfg OF test5 IS
	FOR testbench_arch
	END FOR;
END ctrl_cfg;