aa.gfl

xilinx环境下开发vhdl语言串行接口设计

ctrl.ngc
ctrl.ngr
# ModelSim : Simulate Behavioral VHDL Model
test5.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# Bencher Waveform : PDCL (jhdparse)
# XST (Creating Lso File) : 
ctrl.lso
# xst flow : RunXST
ctrl.syr
ctrl.prj
ctrl.sprj
ctrl.ana
ctrl.stx
ctrl.cmd_log
ctrl.ngc
ctrl.ngr
# XST (Creating Lso File) : 
ctrl.lso
# xst flow : RunXST
ctrl.syr
ctrl.prj
ctrl.sprj
ctrl.ana
ctrl.stx
ctrl.cmd_log
ctrl.ngc
ctrl.ngr
# Update Bencher Waveform
__projnav/updateTBW_tcl.rsp
test5.vhw
test5.ano
test5.tfw
# ModelSim : Simulate Behavioral VHDL Model
test5.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# Bencher Waveform : PDCL (jhdparse)
# XST (Creating Lso File) : 
ctrl.lso
# xst flow : RunXST
ctrl.syr
ctrl.prj
ctrl.sprj
ctrl.ana
ctrl.stx
ctrl.cmd_log
ctrl.ngc
ctrl.ngr
# Update Bencher Waveform
__projnav/updateTBW_tcl.rsp
test5.vhw
test5.ano
test5.tfw
# Bencher Waveform : PDCL (jhdparse)
# XST (Creating Lso File) : 
ctrl.lso
# xst flow : RunXST
ctrl.syr
ctrl.prj
ctrl.sprj
ctrl.ana
ctrl.stx
ctrl.cmd_log
ctrl.ngc
ctrl.ngr
# Update Bencher Waveform
__projnav/updateTBW_tcl.rsp
test5.vhw
test5.ano
test5.tfw
# ModelSim : Simulate Behavioral VHDL Model
test5.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
test5.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
test5.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# Bencher Waveform : PDCL (jhdparse)
# XST (Creating Lso File) : 
ctrl.lso
# xst flow : RunXST
ctrl.syr
ctrl.prj
ctrl.sprj
ctrl.ana
ctrl.stx
ctrl.cmd_log
ctrl.ngc
ctrl.ngr
# XST (Creating Lso File) : 
ctrl.lso
# xst flow : RunXST
ctrl.syr
ctrl.prj
ctrl.sprj
ctrl.ana
ctrl.stx
ctrl.cmd_log
ctrl.ngc
ctrl.ngr
# Update Bencher Waveform
__projnav/updateTBW_tcl.rsp
test5.vhw
test5.ano
test5.tfw
# ModelSim : Simulate Behavioral VHDL Model
test5.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
test5.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
test5.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
test5.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
test5.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
test5.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
test5.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# Bencher Waveform : PDCL (jhdparse)
# Bencher Waveform : PDCL (jhdparse)
# XST (Creating Lso File) : 
serial.lso
# xst flow : RunXST
serial.syr
serial.prj
serial.sprj
serial.ana
serial.stx
serial.cmd_log
bps.ngc
xmit.ngc
rev.ngc
ctrl.ngc
bps.ngr
xmit.ngr
rev.ngr
ctrl.ngr
# XST (Creating Lso File) : 
serial.lso
# xst flow : RunXST
serial.syr
serial.prj
serial.sprj
serial.ana
serial.stx
serial.cmd_log
bps.ngc
bps.ngr
# XST (Creating Lso File) : 
serial.lso
# xst flow : RunXST
serial.syr
serial.prj
serial.sprj
serial.ana
serial.stx
serial.cmd_log
bps.ngc
bps.ngr
# XST (Creating Lso File) : 
serial.lso
# xst flow : RunXST
serial.syr
serial.prj
serial.sprj
serial.ana
serial.stx
serial.cmd_log
bps.ngc
bps.ngr
# XST (Creating Lso File) : 
serial.lso
# xst flow : RunXST
serial.syr
serial.prj
serial.sprj
serial.ana
serial.stx
serial.cmd_log
bps.ngc
bps.ngr
# XST (Creating Lso File) : 
serial.lso
# xst flow : RunXST
serial.syr
serial.prj
serial.sprj
serial.ana
serial.stx
serial.cmd_log
bps.ngc
serial.ngc
bps.ngr
serial.ngr
# XST (Creating Lso File) : 
serial.lso
# xst flow : RunXST
serial.syr
serial.prj
serial.sprj
serial.ana
serial.stx
serial.cmd_log
bps.ngc
xmit.ngc
serial.ngc
bps.ngr
xmit.ngr
serial.ngr
# XST (Creating Lso File) : 
serial.lso
# xst flow : RunXST
serial.syr
serial.prj
serial.sprj
serial.ana
serial.stx
serial.cmd_log
bps.ngc
xmit.ngc
serial.ngc
bps.ngr
xmit.ngr
serial.ngr
# XST (Creating Lso File) : 
serial.lso
# xst flow : RunXST
serial.syr
serial.prj
serial.sprj
serial.ana
serial.stx
serial.cmd_log
bps.ngc
xmit.ngc
serial.ngc
bps.ngr
xmit.ngr
serial.ngr
# XST (Creating Lso File) : 
serial.lso
# xst flow : RunXST
serial.syr
serial.prj
serial.sprj
serial.ana
serial.stx
serial.cmd_log
bps.ngc
xmit.ngc
rev.ngc
ctrl.ngc
serial.ngc
bps.ngr
xmit.ngr
rev.ngr
ctrl.ngr
serial.ngr
# XST (Creating Lso File) : 
serial.lso
# xst flow : RunXST
serial.syr
serial.prj
serial.sprj
serial.ana
serial.stx
serial.cmd_log
bps.ngc
xmit.ngc
rev.ngc
serial.ngc
bps.ngr
xmit.ngr
rev.ngr
serial.ngr
# XST (Creating Lso File) : 
serial.lso
# xst flow : RunXST
serial.syr
serial.prj
serial.sprj
serial.ana
serial.stx
serial.cmd_log
bps.ngc
xmit.ngc
rev.ngc
serial.ngc
bps.ngr
xmit.ngr
rev.ngr
serial.ngr
# XST (Creating Lso File) : 
serial.lso
# xst flow : RunXST
serial.syr
serial.prj
serial.sprj
serial.ana
serial.stx
serial.cmd_log
bps.ngc
xmit.ngc
serial.ngc
bps.ngr
xmit.ngr
serial.ngr
# XST (Creating Lso File) : 
serial.lso
# xst flow : RunXST
serial.syr
serial.prj
serial.sprj
serial.ana
serial.stx
serial.cmd_log
bps.ngc
xmit.ngc
ctrl.ngc
serial.ngc
bps.ngr
xmit.ngr
ctrl.ngr
serial.ngr
# XST (Creating Lso File) : 
ctrl.lso
# xst flow : RunXST
ctrl.syr
ctrl.prj
ctrl.sprj
ctrl.ana
ctrl.stx
ctrl.cmd_log
ctrl.ngc
ctrl.ngr
# XST (Creating Lso File) : 
serial.lso
# xst flow : RunXST
serial.syr
serial.prj
serial.sprj
serial.ana
serial.stx
serial.cmd_log
bps.ngc
xmit.ngc
rev.ngc
ctrl.ngc
serial.ngc
bps.ngr
xmit.ngr
rev.ngr
ctrl.ngr
serial.ngr
# XST (Creating Lso File) : 
serial.lso
# xst flow : RunXST
serial.syr
serial.prj
serial.sprj
serial.ana
serial.stx
serial.cmd_log
bps.ngc
xmit.ngc
rev.ngc
serial.ngc
bps.ngr
xmit.ngr
rev.ngr
serial.ngr
# XST (Creating Lso File) : 
serial.lso
# xst flow : RunXST
serial.syr
serial.prj
serial.sprj
serial.ana
serial.stx
serial.cmd_log
bps.ngc
xmit.ngc
rev.ngc
ctrl.ngc
serial.ngc
bps.ngr
xmit.ngr
rev.ngr
ctrl.ngr
serial.ngr
# XST (Creating Lso File) : 
serial.lso
# xst flow : RunXST
serial.syr
serial.prj
serial.sprj
serial.ana
serial.stx
serial.cmd_log
bps.ngc
xmit.ngc
rev.ngc
ctrl.ngc
serial.ngc
bps.ngr
xmit.ngr
rev.ngr
ctrl.ngr
serial.ngr
# XST (Creating Lso File) : 
serial.lso
# xst flow : RunXST
serial.syr
serial.prj
serial.sprj
serial.ana
serial.stx
serial.cmd_log
bps.ngc
xmit.ngc
rev.ngc
ctrl.ngc
serial.ngc
bps.ngr
xmit.ngr
rev.ngr
ctrl.ngr
serial.ngr
# ProjNav -> New Source -> TBW
F:\aa\__projnav\hb_cmds
# Bencher Waveform : PDCL (jhdparse)
# Bencher Waveform : PDCL (jhdparse)
# Update Bencher Waveform
__projnav/updateTBW_tcl.rsp
test.vhw
test.ano
test.tfw
# ModelSim : Simulate Behavioral VHDL Model
test.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
test.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# Bencher Waveform : PDCL (jhdparse)
# XST (Creating Lso File) : 
bps.lso
# xst flow : RunXST
bps.syr
bps.prj
bps.sprj
bps.ana
bps.stx
bps.cmd_log
bps.ngc
bps.ngr
# ModelSim : Simulate Behavioral VHDL Model
test.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# Bencher Waveform : PDCL (jhdparse)