serial.vhdl

来自「xilinx环境下开发vhdl语言串行接口设计」· VHDL 代码 · 共 81 行

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity serial is
 port(
      rst : std_logic;
		clk : std_logic;
	   npreq,nprd,npwr:in std_logic;
	   ioab:in std_logic_vector(1 downto 0);
	   iodb :inout std_logic_vector(7 downto 0);
		rxd : in std_logic;
		txd : out std_logic);
end serial;

architecture Behavioral of serial is
	 component xmit is
	  Port ( clrn : in std_logic;
	        tdata : in std_logic_vector(7 downto 0);
           clktr : in std_logic;
           txd : out std_logic;
           xmitting : out std_logic;
           done_xmitting : out std_logic;
           enclk : out std_logic);
     end component;

	  component rev is
	    Port ( clrn: in std_logic;
           clktr : in std_logic;
           rxd : in std_logic;
           rdata : out std_logic_vector(7 downto 0);
           rcving : out std_logic;
           done_rcving : out std_logic;
           enclk : out std_logic);
      end component;

		component bps is
		  Port ( clk : in std_logic;
           enclk : in std_logic;
           clktr : out std_logic);
      end component;

		component ctrl is
		   Port ( rst : in std_logic;
           npreq : in std_logic;
           nprd : in std_logic;
           npwr : in std_logic;
           ioab : in std_logic_vector(1 downto 0);
           iodb : inout  std_logic_vector(7 downto 0);
           tdata : out std_logic_vector(7 downto 0);
           rdata : in std_logic_vector(7 downto 0);
           rcving : in std_logic;
           done_rcving : in std_logic;
           xmitting : in std_logic;
           done_xmitting : in std_logic;
			  sclrn : out std_logic);
       end component;
	 signal  aclrn: std_logic;
	 signal  xmitt,rcv,drcv,dxmitt  : std_logic; 
	 signal  sdata,data : std_logic_vector(7 downto 0);
	 signal  rcvclk,xmittclk : std_logic;
	 signal  rable,xable : std_logic;
begin
	  u1:	bps  port map(clk,xable,xmittclk);

	  u2 : bps port map(clk,rable,rcvclk);
	 
	  u3:	xmit  port map(rst,data,xmittclk,txd,xmitt,dxmitt,xable);
	  
	  u4:	rev  port map(aclrn,rcvclk,rxd,sdata,rcv,drcv,rable);

     u5:   ctrl port map(rst,npreq,nprd,npwr,ioab,iodb,data,sdata,rcv,drcv,xmitt,dxmitt,aclrn);

end Behavioral;