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来自「xilinx环境下开发vhdl语言串行接口设计」· 代码 · 共 78 行

# Reading C:/Modeltech_xe/tcl/vsim/pref.tcl 
# do test.fdo 
# ** Warning: (vlib-34) Library already exists at "work".
# Model Technology ModelSim XE vcom 5.6a Compiler 2002.04 Apr 29 2002
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Compiling entity bps
# -- Compiling architecture main of bps
# Model Technology ModelSim XE vcom 5.6a Compiler 2002.04 Apr 29 2002
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Compiling entity xmit
# -- Compiling architecture main of xmit
# Model Technology ModelSim XE vcom 5.6a Compiler 2002.04 Apr 29 2002
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Compiling entity rev
# -- Compiling architecture main of rev
# Model Technology ModelSim XE vcom 5.6a Compiler 2002.04 Apr 29 2002
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Compiling entity ctrl
# -- Compiling architecture main of ctrl
# Model Technology ModelSim XE vcom 5.6a Compiler 2002.04 Apr 29 2002
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Compiling entity serial
# -- Compiling architecture behavioral of serial
# -- Loading entity bps
# -- Loading entity xmit
# -- Loading entity rev
# -- Loading entity ctrl
# Model Technology ModelSim XE vcom 5.6a Compiler 2002.04 Apr 29 2002
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package textio
# -- Loading package std_logic_textio
# -- Compiling entity test
# -- Compiling architecture testbench_arch of test
# -- Loading entity serial
# -- Compiling configuration serial_cfg
# -- Loading entity test
# -- Loading architecture testbench_arch of test
# vsim -lib work -t 1ps test 
# Loading C:/Modeltech_xe/win32xoem/../std.standard
# Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_1164(body)
# Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_arith(body)
# Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_unsigned(body)
# Loading C:/Modeltech_xe/win32xoem/../std.textio(body)
# Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_textio(body)
# Loading work.test(testbench_arch)
# Loading work.serial(behavioral)
# Loading work.bps(main)
# Loading work.xmit(main)
# Loading work.rev(main)
# Loading work.ctrl(main)
# .wave
# .structure
# .signals
# ** Failure: Simulation successful (not a failure).  No problems detected. 
#    Time: 1810 ns  Iteration: 0  Instance: /test
# Break at test.vhw line 180
# Simulation Breakpoint: Break at test.vhw line 180
# MACRO ./test.fdo PAUSED at line 17
destroy .wave